Datasheet

I
2
C Serial Port Operation
I
2
C Slave Address
The device’s slave address byte is D0h. The first byte
sent to the device includes the device identifier and the
R/W bit (
Figure4). The device address sent by the I
2
C
master must match the address assigned to the device.
I
2
C Denitions
The following terminology is commonly used to describe
I
2
C data transfers.
Master Device: The master device controls the slave
devicesonthebus.ThemasterdevicegeneratesSCL
clockpulsesandSTARTandSTOPconditions.
Slave Devices: Slave devices send and receive data at
the master’s request.
Bus Idle or Not Busy: Time between STOP and
STARTconditionswhenbothSDAandSCLareinac-
tiveandintheirlogic-highstates.Whenthebusisidle
it often initiates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
TransitioningSDAfromhightolowwhileSCLremains
high generates a START condition. See Figure 1 for
applicable timing.
STOP Condition:
ASTOPconditionisgeneratedbythe
master to end a data transfer with a slave. Transitioning
SDAfromlowtohighwhileSCLremainshighgenerates
aSTOPcondition.SeeFigure1 for applicable timing.
Repeated START Condition
: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it immediately initiates a new data
transfer following the current one. Repeated STARTs
are commonly used during read operations to identify
a specific memory address to begin a data transfer.
A repeated START condition is issued identically to a
normal START condition. See Figure 1 for applicable
timing.
Bit Write: Transitions of SDA must occur during the low
stateofSCL.ThedataonSDAmustremainvalidand
unchangedduringtheentirehighpulseofSCLplusthe
setup and hold time requirements (see Figure1). Data is
shiftedintothedeviceduringtherisingedgeoftheSCL.
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (see
Figure1)beforethenextrisingedgeofSCL
during a bit read. The device shifts out each bit of data
onSDAatthefallingedgeofthepreviousSCLpulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCLclockpulsesincludingwhenitisreadingbitsfrom
the slave.
Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th
bit transmitted during a byte transfer. The device receiv-
ing data (the master during a read or the slave during
a write operation) performs an ACK by transmitting a
zeroduringthe9thbit.AdeviceperformsaNACKby
transmitting a one during the 9th bit. Timing for the ACK
and NACK is identical to all other bit writes. An ACK is
the acknowledgment that the device is properly receiv-
ing data. A NACK is used to terminate a read sequence
or as an indication that the device is not receiving data.
Byte Write:
Abytewriteconsistsof8bitsofinforma-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgment from the
slavetothemaster.The8bitstransmittedbythemas-
ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.
Byte Read:
Abytereadisan8-bitinformationtransfer
from the slave to the master plus a 1-bit ACK or NACK
fromthemastertotheslave.The8bitsofinformation
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
Figure 4. Slave Address Byte
1 1 10 R/W000
MSB
LSB
READ/
WRITE BIT
DEVICE
IDENTIFIER
DS1339B Low-Current, I
2
C, Serial Real-Time Clock
For High-ESR Crystals
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