Datasheet

DS1338 I
2
C RTC with 56-Byte NV RAM
5 of 16
Figure 2. Timing Diagram
Figure 3. Block Diagram
RAM
(56 X 8)
SERIAL BUS
INTERFACE
AND ADDRESS
REGISTER
CONTROL
LOGIC
1Hz
1Hz/4.096kHz/8.192kHz/32.768kHz MUX/
BUFFER
USER BUFFER
(7 BYTES)
CLOCK,
CALENDAR,
AND CONTROL
REGISTERS
"C" VERSION ONLY
POWER
CONTROL
DS1338
X1
C
L
C
L
X2
SDA
SCL
SQW/OUT
V
CC
GND
V
BAT
Oscillator
and divider
N