Datasheet

DS1318
Parallel-Interface Elapsed Time Counter
2 _____________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(V
CC
= V
CC(MIN)
to V
CC(MAX)
, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on any Pin Relative to Ground ......-0.3V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (soldering, 10s) .................................+260°C
Soldering Temperature (reflow) .......................................+260°C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP (multilayer board)
Junction-to-Ambient Thermal Resistance (θ
JA
) ............72°C/W
Junction-to-Case Thermal Resistance (θ
JC
) .................13°C/W
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
CC
(Note 3) 3.0 3.3 3.6 V
Battery Voltage V
BAT
(Note 3) 1.6 3.3 3.7 V
Logic 1 Voltage V
IH
(Note 3)
0.7 x
V
CC
V
CC
+
0.5
V
Logic 0 Voltage V
IL
(Note 3) -0.5
+0.3 x
V
CC
V
DC ELECTRICAL CHARACTERISTICS
(V
CC
= V
CC(MIN)
to V
CC(MAX)
, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Logic 0 Output Current
(V
OL
= 0.15 x V
CC
)
I
OL
3 mA
Logic 1 Output Current
(V
OH
= 0.85 x V
CC
)
I
OH
1 mA
SQW, INT Logic 0 Output
(V
OL
= 0.15 x V
CC
)
I
OLSI
5 mA
Input Leakage I
LI
(Note 4) 1 μA
I/O Leakage I
LO
(Note 5) -1 +1 μA
Active Supply Current I
CCA
(Note 6) 10 mA
Standby Current I
CCS
(Note 7) 100 150 μA
Battery Input-Leakage Current I
BATLKG
10 100 nA
Power-Fail Voltage V
PF
(Note 3) 2.70 2.97 V
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial
.