Datasheet
Table Of Contents
- BENEFITS AND FEATURES
- ORDERING INFORMATION
- DESCRIPTION
- Figure 1. BLOCK DIAGRAM
- CLOCK ACCURACY
- CLOCK, CALENDAR, AND ALARM
- WRITING TO THE CLOCK REGISTERS
- READING FROM THE CLOCK REGISTERS
- FUNCTION
- BIT7
- 1Hz (1Hz Output Enable) – This bit controls the 1Hz output. When this bit is a logic 1, the 1Hz output is enabled. When this bit is a logic 0, the 1Hz output is high-Z.
- AIE0 (Alarm Interrupt Enable 0) – When set to a logic 1, this bit permits the interrupt 0 request flag (IRQF0) bit in the status register to assert . When the AIE0 bit is set to logic 0, the IRQF0 bit does not initiate the signal.
- AIE1 (Alarm Interrupt Enable 1) – When set to a logic 1, this bit permits the interrupt 1 request flag (IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does not initiate an interrupt signal, and the...
- STATUS REGISTER (READ 10H)
- TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)
- Table 3. TRICKLE CHARGER RESISTOR AND DIODE SELECT
- POWER CONTROL
- Figure 4. POWER-SUPPLY CONFIGURATIONS
- SERIAL INTERFACE
- SERIAL PERIPHERAL INTERFACE (SPI)
- Figure 5. SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER
- CLOCK POLARITY (CPOL)
- ADDRESS AND DATA BYTES
- Figure 6. SPI SINGLE-BYTE WRITE
- Figure 7. SPI SINGLE-BYTE READ
- Figure 8. SPI MULTIPLE-BYTE BURST TRANSFER
- BIT7
- READING AND WRITING IN BURST MODE
- Burst mode is similar to a single-byte read or write, except that CE is kept high and additional SCLK cycles are sent until the end of the burst. The clock registers and the user RAM may be read or written in burst mode. When accessing the clock regis...
- 3-WIRE INTERFACE
- Figure 9. 3-WIRE SINGLE BYTE TRANSFER
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED DC OPERATING CONDITIONS (TA = Over the operating range, unless otherwise specified.)
- CAPACITANCE (TA = +25C)
- Figure 10. TIMING DIAGRAM: 3-WIRE READ DATA TRANSFER
- Figure 11. TIMING DIAGRAM: 3-WIRE WRITE DATA TRANSFER
- SPI AC ELECTRICAL CHARACTERISTICS (TA = Over the operating range, unless otherwise specified.)
- Figure 12. TIMING DIAGRAM: SPI READ DATA TRANSFER
- Figure 13. TIMING DIAGRAM: SPI WRITE DATA TRANSFER
- NOTES:
- REVISION HISTORY
- SYMBOL
- PARAMETER
- SYMBOL
- SYMBOL
- PARAMETER
- SYMBOL
- PARAMETER
DS1306
NOTES:
1) I
CC1T
and I
CC2T
are specified with CE set to a logic 0.
2) I
CC1A
and I
CC2A
are specified with CE = V
CC
, SCLK = 2MHz at V
CC
= 5V; SCLK = 500kHz at V
CC
=
2.0V, V
IL
= 0V, V
IH
= V
CC
.
3) Measured at V
IH
= 2.0V or V
IL
= 0.8V and 10ms maximum rise and fall time.
4) Measured with 50pF load.
5) Measured at V
OH
= 2.4V or V
OL
= 0.4V.
6) V
CC
= V
CC1
, when V
CC1
> V
CC2
+ 0.2V (typical); V
CC
= V
CC2
, when V
CC2
> V
CC1
.
7) V
CC2
= 0V.
8) V
CC1
= 0V.
9) V
CC1
< V
BAT
.
10) V
CCIF
must be less than or equal to the largest of V
CC1
, V
CC2
, and V
BAT
.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
16 PDIP P16+1
21-0043
20 TSSOP U20+1
21-0066
21 of 22