Datasheet
Table Of Contents
- BENEFITS AND FEATURES
- ORDERING INFORMATION
- DESCRIPTION
- Figure 1. BLOCK DIAGRAM
- CLOCK ACCURACY
- CLOCK, CALENDAR, AND ALARM
- WRITING TO THE CLOCK REGISTERS
- READING FROM THE CLOCK REGISTERS
- FUNCTION
- BIT7
- 1Hz (1Hz Output Enable) – This bit controls the 1Hz output. When this bit is a logic 1, the 1Hz output is enabled. When this bit is a logic 0, the 1Hz output is high-Z.
- AIE0 (Alarm Interrupt Enable 0) – When set to a logic 1, this bit permits the interrupt 0 request flag (IRQF0) bit in the status register to assert . When the AIE0 bit is set to logic 0, the IRQF0 bit does not initiate the signal.
- AIE1 (Alarm Interrupt Enable 1) – When set to a logic 1, this bit permits the interrupt 1 request flag (IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does not initiate an interrupt signal, and the...
- STATUS REGISTER (READ 10H)
- TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)
- Table 3. TRICKLE CHARGER RESISTOR AND DIODE SELECT
- POWER CONTROL
- Figure 4. POWER-SUPPLY CONFIGURATIONS
- SERIAL INTERFACE
- SERIAL PERIPHERAL INTERFACE (SPI)
- Figure 5. SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER
- CLOCK POLARITY (CPOL)
- ADDRESS AND DATA BYTES
- Figure 6. SPI SINGLE-BYTE WRITE
- Figure 7. SPI SINGLE-BYTE READ
- Figure 8. SPI MULTIPLE-BYTE BURST TRANSFER
- BIT7
- READING AND WRITING IN BURST MODE
- Burst mode is similar to a single-byte read or write, except that CE is kept high and additional SCLK cycles are sent until the end of the burst. The clock registers and the user RAM may be read or written in burst mode. When accessing the clock regis...
- 3-WIRE INTERFACE
- Figure 9. 3-WIRE SINGLE BYTE TRANSFER
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED DC OPERATING CONDITIONS (TA = Over the operating range, unless otherwise specified.)
- CAPACITANCE (TA = +25C)
- Figure 10. TIMING DIAGRAM: 3-WIRE READ DATA TRANSFER
- Figure 11. TIMING DIAGRAM: 3-WIRE WRITE DATA TRANSFER
- SPI AC ELECTRICAL CHARACTERISTICS (TA = Over the operating range, unless otherwise specified.)
- Figure 12. TIMING DIAGRAM: SPI READ DATA TRANSFER
- Figure 13. TIMING DIAGRAM: SPI WRITE DATA TRANSFER
- NOTES:
- REVISION HISTORY
- SYMBOL
- PARAMETER
- SYMBOL
- SYMBOL
- PARAMETER
- SYMBOL
- PARAMETER
DS1306
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE TOP MARK*
DS1306
0°C to +70°C
16 DIP (300 mils)
DS1306
DS1306+
0°C to +70°C
16 DIP (300 mils)
DS1306 +
DS1306N
-40°C to +85°C
16 DIP (300 mils)
DS1306N
DS1306N+
0°C to +70°C
16 DIP (300 mils)
DS1306N +
DS1306E
0°C to +70°C
20 TSSOP (173 mils)
DS1306
DS1306E+
0°C to +70°C
20 TSSOP (173 mils)
DS1306 +
DS1306EN
-40°C to +85°C
20 TSSOP (173 mils)
DS1306N
DS1306EN+
-40°C to +85°C
20 TSSOP (173 mils)
DS1306N +
DS1306EN/T&R
-40°C to +85°C
20 TSSOP (173 mils)
DS1306N
DS1306EN+T&R
-40°C to +85°C
20 TSSOP (173 mils)
DS1306N +
DS1306E/T&R
0°C to +70°C
20 TSSOP (173 mils)
DS1306
DS1306E+T&R
0°C to +70°C
20 TSSOP (173 mils)
DS1306 +
+Denotes a lead(Pb)-free/RoHS-compliant package
T&R = Tape and reel.
*An “N” on the top mark indicates an industrial device.
PIN DESCRIPTION
PIN
NAME FUNCTION
TSSOP
DIP
1 1 V
CC2
Backup Power Supply. This is the secondary power supply pin. In systems
using the trickle charger, the rechargeable energy source is connected to this
pin.
2 2 V
BAT
Battery Input for Any Standard +3V Lithium Cell or Other Energy
Source. If not used, V
BAT
must be connected to ground. Diodes must not be
placed in series between V
BAT
and the battery, or improper operation will
result. UL recognized to ensure against reverse charging current when used
in conjunction with a lithium battery. See “Conditions of Acceptability” at
www.maxim-ic.com/TechSupport/QA/ntrl.htm.
3 3 X1
Connections for Standard 32.768kHz Quartz Crystal. The internal
oscillator is designed for operation with a crystal having a specified load
capacitance of 6pF. For more information on crystal selection and crystal
layout considerations, refer to Application Note 58, “Crystal Considerations
with Dallas Real-Time Clocks.” The DS1306 can also be driven by an
external 32.768kHz oscillator. In this configuration, the X1 pin is connected
to the external oscillator signal and the X2 pin is floated.
5 4 X2
7 5
INT0
Active-Low Interrupt 0 Output.
The INT0 pin is an active-low output of
the DS1306 that can be used as an interrupt input to a processor. The INT0
pin can be programmed to be asserted by Alarm 0. The INT0 pin remains
low as long as the status bit causing the interrupt is present and the
corresponding interrupt enable bit is set. The INT0 pin operates when the
DS1306 is powered by V
CC1
, V
CC2
, or V
BAT
. The INT0 pin is an open-drain
output and requires an external pullup resistor.
8 6 INT1
Interrupt 1 Output. The INT1 pin is an active-high output of the DS1306
that can be used as an interrupt input to a processor. The INT1 pin can be
programmed to be asserted by Alarm 1. When an alarm condition is present,
the INT1 pin generates a 62.5ms active-high pulse. The INT1 pin operates
only when the DS1306 is powered by V
CC2
or V
BAT
. When active, the INT1
pin is internally pulled up to V
CC2
or V
BAT
. When inactive, the INT1 pin is
2 of 22