Datasheet

DS1267B
LINEARITY MEASUREMENT CONFIGURATION Figure 5
NOTE:
In this setup, a ±2% delta in total resistance R0 to R1 would cause a ±2.5 MI error.
DS1267B ABSOLUTE AND RELATIVE LINEARITY Figure 6
TYPICAL APPLICATION CONFIGURATIONS
Figures 7 and 8 show two typical application configurations for the DS1267B. By connecting the wiper
terminal of the part to a high-impedance load, the effects of the wiper resistance is minimized, since the
wiper resistance can vary from 900Ω to 2000Ω depending on wiper voltage. Figure 7 presents the device
connected in an inverting variable gain amplifier. The gain of the circuit on Figure 7 is given by the
following equation:
A
V
= -n/(255-n); where n = 0 to 255
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224 256
LSB
Tap Position
Linearity vs. Tap Position
INL
DNL
DS1267B
10kΩ
Maxim Integrated ............................................................................................................................................................................................. 6