Datasheet

DS1267B
STACKED CONFIGURATION
The potentiometers of the DS1267B can be connected in series as shown in Figure 3. This is referred to
as the stacked configuration. The stacked configuration allows the user to double the total end-to-end
resistance of the part and the number of steps to 512 (or 9 bits of resolution).
The wiper output for the combined stacked potentiometer will be taken at the S
OUT
pin, which is the
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the S
OUT
output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
shift register. If the stack select bit has value 0, the multiplexed output, S
OUT
, will be that of the
potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, S
OUT
, will be that of the
potentiometer-1 wiper.
STACKED CONFIGURATION Figure 3
CASCADE OPERATION
A feature of the DS1267B is the ability to control multiple devices from a single processor. Multiple
DS1267Bs can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1267B a bit will appear at the C
OUT
output within a maximum delay of 50 nanoseconds.
The stack select bit of the DS1267B will always be the first out the part at the beginning of a transaction.
Additionally the C
OUT
pin is always active regardless of the state of
RST
. This allows one to read the I/O
shift register without changing its value.
CASCADING MULTIPLE DEVICES Figure 4
Maxim Integrated ............................................................................................................................................................................................. 4