Datasheet

DS1085
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External control inputs, CTRL1 and CTRL0, enable or disable the two oscillator outputs. Both outputs
feature a synchronous enable that ensures no output glitches when the output is enabled and a constant
time interval (for a given frequency setting) from an enable signal to the first output transition. These
inputs also can be configured to disable the master oscillator, putting the device into a low-power mode
for power-sensitive applications.
Figure 1. DS1085 BLOCK DIAGRAM
OVERVIEW
A block diagram of the DS1085 is shown in Figure 1. The DS1085 consists of five major components:
§ Master oscillator control DAC
§ Internal master oscillator (66MHz to 133MHz)
§ Prescalers (divide-by-1, 2, 4, or 8)
§ Programmable divider (divide-by-1 to 1025)
§ Control registers
The internal master oscillator provides the reference clock (MCLK), which is fed to the prescalers and
programmable dividers. The frequency of the oscillator can be user-programmed over a two-to-one range
in increments equal to the step size, by means of a 10-bit control DAC. The master oscillator range is
66MHz to 133MHz, which is larger than the range possible with the 10-bit DAC resolution and available
step sizes. Therefore, an additional register (OFFSET) is provided that can be used to select the range of
frequency over which the DAC is used (see Table 1).
0M0 0M1
1M0 1M1