Datasheet

DS1085
19 of 21
9) This indicates the time taken between power-up and the outputs becoming active. An on-chip delay is
intentionally introduced to allow the oscillator to stabilize. t
stab
is equivalent to approximately 8000
clock cycles and hence depends on the programmed clock frequency.
10) Output voltage swings can be impaired at high frequencies combined with high-output loading.
11) After this period, the first clock pulse is generated.
12) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
V
IH MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
13) The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
14) A fast-mode device can be used in a standard mode system, but the requirement t
SU:DAT
> 250ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line at least t
R MAX
+ t
SU:DAT
= 1000ns + 250ns = 1250ns before the SCL line is
released.
15) C
B
—total capacitance of one bus line in picofarads; timing referenced to 0.9V
CC
and 0.1V
CC
.
16) EEPROM write begins after a STOP condition occurs.
17) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow
preconditioning (24hr +125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes
+240 +0/-5°C peak) followed by 1000hr max V
CC
biased 125°C HTOL, 1000 temperature cycles at -
55°C to +125°C, 96hr 130°C/85%RH/5.5V HAST and 168hr 121°C/2 ATM Steam/Unbiased
Autoclave.
Figure 5. MASTER FREQUENCY TEMPERATURE VARIATION
MASTER FREQUENCY TEMPERATURE
VARIATION
-2.00
-1.50
-1.00
-0.50
0.00
0.50
1.00
1.50
2.00
66.00 82.75 99.50 116.25 133.00
MASTER OSCILLATOR FREQUENCY (MHz)
FREQUENCY % CHANGE FROM 25°C