Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsDS1085Z-10+

1 of 21 051506

FEATURES

§ User-Programmable Frequency Synthesizer

§ Programmable From 8.1kHz to 133MHz

§ Dual Synchronous Outputs

§ 8.2MHz to 133MHz Reference Oscillator

Output

§ 8.1kHz to 133MHz Main Oscillator Output

§ Three Resolution Options

§ 2-Wire Serial Interface

§ 0.75% Absolute Accuracy

§ Nonvolatile (NV) Frequency Settings

§ Single 5V Supply

§ No External Timing Components

§ Power-Down Mode

PIN ASSIGNMENT

PIN DESCRIPTION

OUT1 - Main Oscillator Output

OUT0 - Reference Oscillator Output

- Power-Supply Voltage

GND - Ground

CTRL1 - Control Pin for OUT1

CTRL0 - Control Pin for OUT0

SDA - 2-Wire Serial Data Input/Output

SCL - 2-Wire Serial Clock

ORDERING INFORMATION

DEVICE PACKAGE

STEP

SIZE

OSCILLATOR

OUTPUT RANGE

DS1085Z-10 150mil SO 10kHz 8.1kHz to 133MHz

DS1085Z-25 150mil SO 25kHz 8.1kHz to 133MHz

DS1085Z-50 150mil SO 50kHz 8.1kHz to 133MHz

DESCRIPTION

The DS1085 is a dual-output frequency synthesizer requiring no external timing components for

operation. It can be used as a standalone oscillator or as a dynamically programmed, processor-controlled

peripheral device. An internal master oscillator can be programmed from 66MHz to 133MHz with three

resolution options of 10kHz, 25kHz, and 50kHz. A programmable, 3-bit prescaler (divide-by-1, 2, 4, or 8)

permits the generation of a reference oscillator output (OUT0) from the master, ranging from 8.2MHz to

133MHz. A second independent prescaler and a 1-to-1025 divider allows the generation of a main

oscillator output (OUT1) from 8.1kHz to 133MHz. The two outputs, although synchronous with the

master, can be independently programmed. The combination of programmable master oscillator,

prescalers, and dividers allows the generation of thousands of user-specified frequencies. All master

oscillator, prescaler, and divider settings are stored in NV (EEPROM) memory, providing a default value

on power-up that allows it to be used as a standalone oscillator. A 2-wire serial interface allows in-circuit,

on-the-fly programming of the master oscillator, prescalers (P0 and P1), and divider (N). This allows

dynamic frequency modification, if required, or, for fixed-frequency applications, the DS1085 can be

used with factory- or user-programmed values.

DS1085

EconOscillator Frequency Synthesize

www.maxim-ic.com

SO (150mil)

SCL

CTRL0

CTRL1

OUT1

OUT0

GND

EconOscillator is a trademark of Dallas Semiconductor.

Summary of content (21 pages)

PAGE 1
DS1085 EconOscillator Frequency Synthesizer www.maxim-ic.com PIN ASSIGNMENT FEATURES § § § § § § § § § § § § User-Programmable Frequency Synthesizer Programmable From 8.1kHz to 133MHz Dual Synchronous Outputs 8.2MHz to 133MHz Reference Oscillator Output 8.1kHz to 133MHz Main Oscillator Output Three Resolution Options 2-Wire Serial Interface 0.
PAGE 2
DS1085 External control inputs, CTRL1 and CTRL0, enable or disable the two oscillator outputs. Both outputs feature a synchronous enable that ensures no output glitches when the output is enabled and a constant time interval (for a given frequency setting) from an enable signal to the first output transition. These inputs also can be configured to disable the master oscillator, putting the device into a low-power mode for power-sensitive applications. Figure 1.
PAGE 3
DS1085 Table 1. DEVICE COMPARISONS BY PART NUMBER PART NUMBER STEP SIZE (kHz) DAC SPAN (MHz) OFFSET SIZE (MHz) DS1085Z-10 10 10.24 5.12 DS1085Z-25 25 25.60 6.40 DS1085Z-50 50 51.20 6.40 For further description of use of the OFFSET register, see the REGISTER FUNCTIONS section. The master clock can be routed directly to the outputs (OUT0 and OUT1) or through separate prescalers (P0 and P1). In the case of OUT1, an additional programmable divider (N) can be used to generate frequencies down to 8.1kHz.
PAGE 4
DS1085 Table 2. DEVICE MODE USING OUT0 EN0 (BIT) SEL0 (BIT) PDN0 (BIT) CTRL0 OUT0 CTRL0 DEVICE (PIN) (PIN) FUNCTION MODE 1 High-Z Power-Down* Power-Down*** 0 0 0 0 High-Z Active Mux Select 1 MCLK/M 0 1 0 Active 0 MCLK Output Enable 1 High-Z 1 0 0 Active 0 MCLK 1 High-Z Output Enable 1 1 0 Active** 0 MCLK/M Power-Down 1 High-Z Power-Down X 0 1 0 MCLK Active 1 High-Z Power-Down Power-Down X 1 1 0 MCLK/M Active *This mode is for applications where OUT0 is not used, but CTRL0 is used as a device shutdown.
PAGE 5
DS1085 REGISTER FUNCTIONS The user-programmable registers can be used to determine the mode of operation (MUX), operating frequency (DAC, OFFSET, DIV), and bus settings (ADDR). The functions of the registers are described in this section, but details of how these registers are programmed can be found in a later section. The register settings are nonvolatile, with the values being stored automatically or as required in EEPROM when the registers are programmed through the SDA and SCL pins.
PAGE 6
DS1085 Table 6. FREQUENCY vs. OFFSET DS1085Z-10 DS1085Z-25 DS1085Z-50 FREQUENCY FREQUENCY FREQUENCY RANGE RANGE RANGE OS - 10 — — — OS - 9 — — — OS - 8 — — — OS - 7 — — — OS - 6 61.4 to 71.6 51.2 to 76.8 38.4 to 89.6 OS - 5 66.5 to 76.8 57.6 to 83.2 44.8 to 96.0 OS - 4 71.6 to 81.9 64.0 to 89.6 51.2 to 102.4 OS - 3 76.7 to 87.0 70.4 to 96.0 57.6 to 108.8 OS - 2 81.9 to 92.1 76.8 to 102.4 64.0 to 115.2 OS - 1 87.0 to 97.2 83.2 to 108.8 70.4 to 121.6 OS* 92.1 to 102.3 89.6 to 115.2 76.8 to 128.0 OS + 1 97.
PAGE 7
DS1085 The functions of the individual bits are described in the following paragraphs. DIV1 (Default Setting = 0) This bit allows the output of the prescaler P1 to be routed directly to the OUT1 pin (DIV1 = 1). In this condition, the N divider is bypassed so the programmed value of N is ignored. If DIV1 = 0, the N divider functions normally. EN0 (Default Setting = 1) If EN0 = 1 and PDN0 = 0, the CTRL0 pin functions as an output enable for OUT0, the frequency of the output being determined by the SEL0 bit.
PAGE 8
DS1085 Table 7a. PRESCALER P0 DIVISOR M SETTINGS 0M1 0M0 0 0 0 1 1 0 1 1 *Factory Default Setting PRESCALER P0 DIVISOR “M” 1* 2 4 8 Table 7b. PRESCALER P1 DIVISOR M SETTINGS 1M1 1M0 PRESCALER P1 DIVISOR “M” 0 0 1* 0 1 2 1 0 4 1 1 8 *Factory Default Setting NOTE: When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case for situations when OUT0 is not used. Under these conditions all the circuitry associated with OUT0 is powered down. OUT0 is powered down (see Table 2).
PAGE 9
DS1085 N The DIV word sets the programmable divider. These 10 bits (N0–N9) determine the value of the programmable divider (N). The range of divisor values is from two to 1025, and is equal to the programmed value of N plus 2 (see Table 8). Table 8. PROGRAMMABLE DIVISOR N VALUES BIT VALUE 00000000 00XXXXXX 00000000 01XXXXXX — — — — 11111111 11XXXXXX *Factory Default Setting DIVISOR (N) 2* 3 — — — — 1025 ADDR BYTE (Address 0Dh) MSB — X NAME Factory Default X = Don’t care.
PAGE 10
DS1085 COMMAND SET Data and control information is read from and written to the DS1085 in the format shown in Figure 3. To write to the DS1085, the master issues the slave address of the DS1085 and the R/ W bit is set to 0. After receiving an acknowledge, the bus master provides a command protocol. After receiving this protocol, the DS1085 issues an acknowledge, and then the master can send data to the DS1085.
PAGE 11
DS1085 Access RANGE [37h] If R/ W is 1, the next data bytes read are the values stored in the RANGE register. This register has a 14bit value. The upper eight bits are sent first, followed by a second byte that contains the five LSBs of the register value in the most significant positions of the data byte. The upper five MSBs of the first byte contain the OS value for the frequency adjust Table 6. The register is read-only.
PAGE 12
DS1085 2-WIRE SERIAL DATA BUS The DS1085 communicates through a 2-wire serial interface. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus.
PAGE 13
DS1085 A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figure 2. DATA TRANSFER ON 2-WIRE SERIAL BUS Figures 2, 3, and 4 detail how data transfer is accomplished on the 2-wire bus.
PAGE 14
DS1085 SLAVE ADDRESS A control byte is the first byte received following the START condition from the master device. The control byte consists of a 4-bit control code; for the DS1085, this is set as 1011 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). The address bits to which the DS1085 responds are factory set to 000, but can be altered by writing new values to the ADDR register.
PAGE 15
DS1085 Figure 4.
PAGE 16
DS1085 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -0.5V to +6.0V 0°C to +70°C -55°C to +125°C See IPC/JEDEC J-STD-020A * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 17
DS1085 MASTER OSCILLATOR CHARACTERISTICS (VCC = 5V ±5%, TA = 0°C to +70°C.) PARAMETER Master Oscillator Range SYMBOL fOSC CONDITION MIN 66 -10 Version -25 Version -50 Version VCC = 5V, TA = +25°C TYP MAX 133 97.1 104.6 101.8 Default Master Oscillator Frequency f0 Master Oscillator Frequency Tolerance Df0 f0 Default freq. -0.75 +0.75 -0.75 +0.75 DfV f0 DAC step size Overvoltage range, TA = +25°C default freq. -1.0 +1.0 DAC Step Size -1.0 +1.
PAGE 18
DS1085 AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (VCC = 5V ±5%, TA = 0°C to +70°C.
PAGE 19
DS1085 9) This indicates the time taken between power-up and the outputs becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 8000 clock cycles and hence depends on the programmed clock frequency. 10) Output voltage swings can be impaired at high frequencies combined with high-output loading. 11) After this period, the first clock pulse is generated.
PAGE 20
DS1085 TYPICAL OPERATING CHARACTERISTICS (VCC = 5V ±5%, TA = 0°C to +70°C.) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. VOLTAGE 33.0 30.0 32.5 32.0 25.0 CURRENT (mA) CURRENT (mA) 31.5 31.0 30.5 30.0 20.0 15.0 DS1085-25 29.5 DS1085-50 DS1085-50 10.0 29.0 DS1085-25 28.5 5.0 4.75 28.0 0 10 20 30 40 50 60 70 DS1085-10 4.85 4.95 5.05 5.15 5.25 VOLTAGE (V) TEMPERATURE (°C) SUPPLY CURRENT vs. DIVISOR SUPPLY CURRENT vs. DIVISOR 29 4.75V 27 28 5.
PAGE 21
DS1085 TYPICAL OPERATING CHARACTERISTICS (continued) (VCC = 5V ± 5%, TA = 0°C to +70°C.) SUPPLY CURRENT vs. DIVISOR SUPPLY CURRENT vs. DAC SETTING AND OFFSET 25 24 33 DS1085-25 23 31 DS1085-10 CURRENT (mA) CURRENT (mA) 35 DS1085-50 22 21 29 27 25 23 OS 21 OS + 1 19 20 OS - 1 17 15 19 0 200 400 600 800 0 1000 200 400 600 800 1000 DAC SETTING DIVISOR (N) FREQUENCY % CHANGE vs. SUPPLY VOLTAGE FREQUENCY % CHANGE vs. TEMPERATURE 1.