Datasheet

DG444/DG445
Improved, Quad, SPST Analog Switches
6 _______________________________________________________________________________________
t
OFF
0.8 x V
OUT
V
OUT
0.8 x V
OUT
t
f
< 20ns
t
r
< 20ns
50%
0V
0V
+3V
SWITCH
OUTPUT
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
t
ON
SWITCH
INPUT
LOGIC
INPUT
+3V
IN
+5V
V-
-15V
( )
R
L
C
L
V
OUT
S
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
GND
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
V
OUT
= V
D
R
L
R
L
+ r
DS(ON)
LOGIC
INPUT
V
L
+15V
V+
D
DG444
DG445
Figure 2. Switching Time
Applications Information
General Operation
• Switches are open when power is off.
• IN, D, and S should not exceed V+ or V-, even with
the power off.
• Switch leakage is from each analog switch terminal
to V+ or V-, not to other switch terminals.
Operation with Supply Voltages
Other than ±15V
Using supply voltages other than ±15V will reduce the
analog signal range. The DG444/DG445 switches oper-
ate with ±4.5V to ±20V bipolar supplies or with a +10V
to +30V single supply; connect V- to 0V when operating
with a single supply. Also, all device types can operate
with unbalanced supplies such as +24V and -5V. V
L
must be connected to +5V to be TTL compatible, or to
V+ for CMOS-logic level inputs. The Typical Operating
Characteristics graphs show typical on-resistance with
±20V, ±15V, ±10V, and ±5V supplies. (Switching times
increase by a factor of two or more for operation at ±5V.)
Overvoltage Protection
Proper power-supply sequencing is recommended
for all CMOS devices. Do not exceed the absolute
maximum ratings because stresses beyond the list-
ed ratings may cause permanent damage to the
devices. Always sequence V+ on first, followed by
V
L
, V-, and logic inputs. If power-supply sequenc-
ing is not possible, add two small, external signal
diodes in series with supply pins for overvoltage
protection (Figure 1). Adding diodes reduces the
analog signal range to 1V below V+ and 1V above
V-, but low switch resistance and low leakage char-
acteristics are unaffected. Device operation is
unchanged, and the difference between V+ and V-
should not exceed +44V.
V+
D
V-
S
V
g
Figure 1. Overvoltage Protection Using External Blocking Diodes
_____________________Pin Description
PIN
DIP/SO
THIN QFN
NAME
FUNCTION
1, 16, 9, 8 15, 14, 7, 6 IN1–IN4
Logic Control
Inputs
2, 15, 10, 7 16, 13, 8, 5 D1–D4
Drain Outputs
3, 14, 11, 6 1, 12, 9 4 S1–S4
Source Outputs
42V-
Negative-Supply
Voltage Input
53GND Ground
12 10 VL
Logic-Supply
Voltage Input
13 11 V+
Positive-Supply-
Voltage
Input—Connected
to Substrate
—EPPAD
Exposed Pad
Connect Pad to V+