Datasheet

DG417L/DG418L/DG419L
35Ω, SPST/SPDT, +3V
Logic-Compatible Analog Switches
_______________________________________________________________________________________ 9
Applications Information
Power-Supply
Sequencing-Free Operation
Most CMOS switches require specific power-supply
sequencing in order to prevent device latchup. The
older DG417/DG418/DG419 devices require a proper
power-supply sequence of V+, V
L
, then V-. Otherwise,
it is necessary to add signal diodes to the circuit in
order to prevent potential latchups. The new
DG417L/DG418L/DG419L devices eliminate the need
for a V
L
input and allow any power-up sequence. Do
not exceed the absolute maximum ratings because
stresses beyond the listed ratings may cause perma-
nent damage to the devices.
+3V
0
V
COM
0.9 x V
OUT
LOGIC
INPUT
V-
R
L
300Ω
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO
COM
NC
V+
C
L
35pF
+10V
t
D
IN
V+
V-
V
OUT
LOGIC
INPUT
DG419L
Figure 4. Charge Injection
V
GEN
GND
NC OR
NO
C
L
1nF
V
OUT
V-
V-
V+
N.C.
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = ∆V
OUT
x C
L
COM
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IN
= +3V
DG417L
DG418L
DG419L
V+
Figure 3. DG419L Break-Before-Make Interval
______________________________________Test Circuits/Timing Diagrams (continued)