Datasheet

DG411/DG412/DG413
Improved, Quad,
SPST Analog Switches
_______________________________________________________________________________________ 7
t
r
< 20ns
t
f
< 20ns
50%
0V
LOGIC
INPUT
V-
-15V
R
L
300Ω
D1
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
S (
R
L
)
R
L
+ R
DS(ON)
SWITCH
INPUT
IN1
+3V
t
OFF
0V
SWITCH OUTPUT
0.9 x V
OUT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V
L
V+
C
L
35pF
+5V
+15V
V
OUT
S1
0V
REPEAT TEST FOR IN AND S, FOR LOAD
CONDITIONS, SEE Electrical Characteristics.
DG411
DG412
DG413
50%
0.9 x V
OUT1
+3V
0V
0V
LOGIC
INPUT
SWITCH
OUTPUT 2
(V
O2
)
0V
0.9 x V
OUT2
t
D
t
D
LOGIC
INPUT
V-
-15V
R
L2
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
S2
IN
V
L
S1
V
OUT2
V+
+5V
+15V
C
L2
V
S1
= +10V
V
S2
= +10V
R
L1
V
OUT1
C
L1
R
L
= 300Ω
C
L
= 35pF
D1
D2
SWITCH
OUTPUT 1
(V
O1
)
DG413
Figure 2. Switching-Time
Figure 3. DG413 Break-Before-Make
______________________________________________Timing Diagrams/Test Circuits
V
GEN
GND
D
C
L
V
OUT
-15V
V-
V+
V
OUT
IN
OFF
ON
OFF
ΔV
OUT
Q = (ΔV
OUT
)(C
L
)
S
+5V
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IN
= +3V
+15V
R
GEN
IN
V
L
DG411
DG412
DG413
Figure 4. Charge-Injection