Datasheet
Evaluates: SPI and SMBus/I
2
C-Compatible Parts
CMAXQUSB User’s Guide
5
Connector P3
Connector P3 is a 20-pin, dual-row header that con-
nects to SMBus/I
2
C-based kits. The pinout is compati-
ble with Maxim’s previous SMBus/I
2
C solution, the
MAXSMBus board. See Table 1.
If designing a custom EV kit board, beware: the
ground return system does not connect pin 20.
Connector P4
Connector P4 is a 40-pin, dual-row header that con-
nects to SPI and 8-bit parallel kits. The pinout is com-
patible with Maxim’s previous SPI solution, the
68HC16MODULE board. See Table 2.
GPIO pins K1–K8 and K1’–K15’ must be driven with a
4.7kΩ or lower impedance source to turn around the
bidirectional level translators.
Table 1. Connector P3 Description
*
This +12V signal is provided only for legacy systems and is normally unpowered.
*
This +12V signal is provided only for legacy systems and is normally unpowered.
P3 PIN LABEL FUNCTION
1 VDD Power Supply. 2.5V, 3.3V, or 5V selected by CMAXQUSB VDD select jumper.
2, 4, 5, 6, 8, 10,
12, 14, 16, 18, 19
GND Ground Return
3 SDA SMBus/I
2
C SDA (Data)
7 SCL SMBus/I
2
C SCL (Clock)
9 K6 General-Purpose I/O Designated as K6. Can be used for SMBus SUSPEND output.
11 K1 General-Purpose I/O Designated as K1. Can be used for SMBus ALERT input.
13 K2 General-Purpose I/O Designated as K2
15 K3 General-Purpose I/O Designated as K3
17 K4 General-Purpose I/O Designated as K4
20 +12V*
Optional Unregulated Higher Voltage (7.5V to 16.5V) Power Supply. Enabled only if CMAXQUSB
jumper JU5 is installed and closed, and if external power is applied through connector P1.
Table 2. Connector P4 Description
P4 PIN LABEL GPIO DESIGNATOR FUNCTION
1–4 GND — Ground Return
5, 6 +12V* —
Optional Unregulated Higher Voltage (7.5V to 16.5V) Power Supply.
Enabled only if CMAXQUSB jumper JU5 is closed, and if external power
is applied through connector P1.
7, 8 VDD —
Power Supply. 2.5V, 3.3V, or 5V selected by CMAXQUSB VDD select
jumper.
9 RD K13 when K0 = 1 Active-Low Read Strobe
10 WR K14 when K0 = 1 Active-Low Write Strobe
11 CS0 K15 when K0 = 1 Active-Low Memory Chip-Select Strobe
12, 13, 14 — — No Connection. Reserved for additional memory chip-select strobes.
15 A0 K9 when K0 = 1 Memory Address LSB
16 A1 K10 when K0 = 1 Memory Address
17 A2 K11 when K0 = 1 Memory Address
18 A3 K12 when K0 = 1 Memory Address MSB
19 D0 K1 when K0 = 1 Memory Data LSB