User Manual

UM_8430_005 78Q8430 Driver Manual for ST5100/OS-20 with NexGen TCP/IP Stack
Rev. 1.0 11
3.4 Device Driver Options
Table 4 lists the configuration options for the device driver. Table 5 lists the software default values for
several important 78Q8430 registers and parameters used by the driver. The file Commen.h contains
these default values. To change the default values, make the changes in Commem.h and recompile the
driver. A discussion of these values and how they are chosen follows the table.
Table 4: Device Driver Configuration Options
Option Name Settings Description
DRIVER_MODE INTERRUPT_MODE = 1
POLLING_MODE = 2
Choice of polling mode or interrupt driven.
Polling mode is used only for diagnostics.
TSC_CPU (TSCCPU) ST5100 = 3 Selects target CPU platform for the driver.
Table 5: Driver Default Values for Important 78Q8430 Registers and Parameters
78Q8430 Register
Driver Variable
Name Address
Register Field
Default
Value
MEM_LEAK_OPT_VALUE NA 0x0F
EAR_INT_DELAY_CNT IDCR 0x180 IDC 0x1FFF
WM_INT_FREE_BLOCK Interrupt 0x0F
WM_HR_FREE_BLOCK Headroom 0x04
WM_PAUSE_FREE_BLOCK
WMVR 0x190
Pause 0x09
1. MEM_LEAK_OPT_VALUE: memory leak detection optimal value.
The driver uses the MEM_LEAK_OPT_VALUE parameter to detect a memory leak condition. Several
conditions must be considered when deciding what this value should be.
Theoretically, subtracting the number of memory blocks used by the QUEs (Nq) from the total number of
memory blocks available should equal the number of free blocks. In practice, this may not be exactly true
due to the fact that a dynamic QUE may hold one memory block in reserve. Additionally, one or more
memory blocks may be allocated or de-allocated between the time the number of free blocks are read
and the time it takes to complete the calculation.
Given that there are 127 total memory blocks available and Nf is the number of currently free memory
blocks, the number of unaccounted memory blocks (Na) can be found from the following equation:
Na = 127 – Nq – Nf
If Na is greater than MEM_LEAK_OPT_VALUE, it is an indication that there are some memory leaks and
the driver issues a software reset.
2. EAR_INT_DELAY_CNT: delay in the interrupt if early interrupt is used.
The early receive interrupt has a delay timer feature. This feature is intended to leverage the deep
receive buffer to decrease interrupt handling overhead in the host. Normally, the early receive interrupt is
triggered as soon as any data for a received frame is placed into the receive QUE. The receive interrupt
delay timer delays this interrupt for a programmable amount of time to allow the receive QUE to
accumulate more data. In this way, under conditions of heavy load, several frames can be serviced by a
single receive interrupt.
The interrupt timer is linked to the PHY speed such that the timer value is measured in byte times, or in
other words, a single tick on the interrupt delay timer is equal to the amount of time it would take the PHY
to receive a single byte. The timer does not require that an actual byte be received so the interrupt delay
feature will not cause small frames to be left in the QUE while waiting for more data. Anytime data is