Datasheet

DS_21x3_001 78Q2123/78Q2133 Data Sheet
4.6.3 100BASE-TX System Timing
System timing requirements for 100BASE-TX operation are listed in Table 24-2 of Clause 24 of IEEE
802.3.
Parameter Condition Nom Unit
TX_EN Sampled to first bit of “J” on MDI
output
12 BT
First bit of “J” on MDI input to CRS assert 16 BT
First bit of “T” on MDI input to CRS
de-assert
23 BT
First bit of “J” on MDI input to COL assert 20 BT
First bit of “T” on MDI input to COL
de-assert
24 BT
TX_EN Sampled to CRS assert RPTR = low 6 BT
TX_EN sampled to CRS de-assert RPTR = low 6 BT
4.6.4 10BASE-T System Timing
Parameter Condition Min Nom Max Unit
TX_EN (MII) to TD Delay 6 BT
RD to RXD at (MII) Delay 6 BT
Collision delay 9 BT
SQE test wait 1
Ps
SQE test duration 1
Ps
Jabber on-time* 20 150 ms
Jabber off-time* 250 750 ms
* Guarantee by design. The specifications in the following table are included for information only.
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