Datasheet

78Q2123/78Q2133 Data Sheet DS_21x3_001
3.2 MR1: Status Register
Bits 1.15 through 1.11 reflect the ability of the 78Q2123/78Q2133. They do not reflect any ability changes
made via the MII Management Interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and 0.8 (DUPLEX)in
the Control Register.
Bit Symbol Type Default Description
1.15 100T4 R 0
100BASE-T4 Ability: Reads ‘0’ to indicate the
78Q2123/78Q2133 do not support 100Base-T4 mode.
1.14 100X_F R 1 100BASE-TX Full Duplex Ability:
0 : Not able
1 : Able
1.13 100X_H R 1 100BASE-TX Half Duplex Ability:
0 : Not able
1 : Able
1.12 10T_F R 1 10BASE-T Full Duplex Ability:
0 : Not able
1 : Able
1.11 10T_H R 1 10BASE-T Half Duplex Ability:
0 : Not able
1 : Able
1.10 100T2_F R 0
100BASE-T2 Full Duplex Ability: Reads ‘0’ to indicate the
78Q2123/78Q2133 do not support 100Base-T2 full duplex
mode.
1.9 100T2_H R 0
100BASE-T2 Half Duplex Ability: Reads ‘0’ to indicate the
78Q2123/78Q2133 do not support 100Base-T2 full duplex
mode.
1.8 EXTS R 0 Extended Status Information Availability: Reads ‘0’ to indicate
the 78Q2123/78Q2133 do not support Extended Status
information on MR15.
1.7 RSVD R 0 Reserved
1.6 MFPS R 0 Management Frame Preamble Suppression Support: A “0”
indicates that the 78Q2123/78Q2133 can read management
frames with a preamble.
1.5 ANEGC R 0 Auto-Negotiation Complete: A logic one indicates that the
Auto-Negotiation process has been completed, and that the
contents of registers MR4,5,6 are valid.
1.4 RFAULT RC 0
Remote Fault: A logic one indicates that a remote fault
condition has been detected and it remains set until it is
cleared. This bit can only be cleared by reading this register
(MR1) via the management interface.
1.3 ANEGA R (1) Auto-Negotiation Ability: When set, this bit indicates the
device’s ability to perform Auto-Negotiation. The value of this
bit is determined by the
ANEGEN bit (MR0.12).
1.2 LINK R 0 Link Status: A logic one indicates that a valid link has been
established. If the link status should transition from an OK
status to a NOT-OK status, this bit will become cleared and
remains cleared until it is read.
1.1 JAB RC 0 Jabber Detect: In 10Base-T mode, this bit is set during a
jabber event. After a jabber event, the bit remains set until
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