Datasheet

78M6610+PSU Data Sheet
If the register address pointer has not been set by previous operations, it is necessary to set it issuing a
command as follows:
S Device Address
0 1 2 3 4 5 6
0
S
T
A
R
T
A
C
K
Register Address (n)
2 3 4
5
6
7
S
10
A
C
K
P
S
T
O
P
Random Read: random read operations allow the master to access any register in a random manner. To
perform this operation, the register address must be set as part of the write operation. After the address is
sent, the master generates a START condition following the acknowledge response. This sequence
completes the write operation. The master should issue the control byte again this time, with the R/W bit
set to 1 to indicate a read operation. The 78M6610+PSU will issue the acknowledge response, and
transmit the data.
At the end of the transaction the master will not acknowledge the transfer and generate a STOP
condition.
S Device Address
0 1
2 3
4 5 6
0
S
T
A
R
T
A
C
K
Register Address (n)
2
3 4
5 6 7
S
1
0
A
C
K
S
R
Device Address
0 1
2 3
4 5 6
1
S
T
A
R
T
A
C
K
Data
5
4 3
2 1 0
67
S
N
O
A
C
K
Data
1 2
3 4 5 6 7
A
C
K
0
Data
1 2
3 4
5 6 7
0
This read operation is not limited to 3 bytes but can be extended until the register address pointer
reaches its maximum value.
54 Rev 3