Datasheet

78M6610+PSU Data Sheet
4.3 I
2
C Interface
The 78M6610+PSU has an I
2
C interface available at the SDAI, SDAO, and SCL pins. The interface
supports I
2
C slave mode with a 7-bit address and operates at a data rate up to 400kHz. Figure 4-5 shows
two possible configurations. Configuration A is the standard configuration. The double pin for SDA allows
the isolated configuration B.
V
3
P
3
or
5VDC
SDAi
SDAo
5VDC
I
2C
_GND
SCK
SDAi
SDAo
SCK
A) STANDARD CONFIGURATION
B) ISOLATED CONFIGURATION
5
VDC
SDA
SCK
SDA
SCK
V
3P
3
or 5
VDC
V
3P
3
or
5VDC
Figure 4-5: I
2
C Bus Connection in Standard (A) and Isolated (B) Configuration
The I
2
C interface allows access to read and write registers contained in a 256 word (24-bit) area of the
on-chip RAM. The address of each register specified in Section 3
must be divided by 3 to obtain the
relevant address for the I
2
C access. While access to a single byte is possible, it is highly recommended
that the user access words (or multiple words) of data with each transaction.
The device address of each 78M6610+PSU is configured through the register DevAddr, which defines
address bits 6 through 2 of the device address. Address bits 0 and 1 are configured through pins ADDR1
and SCK/ADDR0 (24-pin package). With the 16-pin package option, the DevAddr register defines
address bits 6 through 1, while bit 0 is configured through the pin SCK/ADDR0.
Rev 3 51