Datasheet

78M6610+PSU Data Sheet
Single Word SPI Writes
The device supplies direct write access to the device RAM memory. To write the RAM the master device
must send a write command to the slave device and then clock out the write data. SSB must be kept
active low for the entire write transaction (command and data). SCK may be interrupted as long as SSB
remains low. ADDR[5:0] is filled with the word address of the write transaction. RAM data contents are
transmitted most significant byte first. ADDR[5:0] cannot exceed 0x3F. RAM words are natively 24 bits
(3 bytes) long.
Byte#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0x01
1
ADDR[5:0]
0x02
2
DATA[23:16] @ ADDR
3
DATA[15:8] @ ADDR
4
DATA[7:0] @ ADDR
Table 4-6. Single Word SPI Write Command and Data (SDI)
The slave SDO remains Hi-Z during a write access.
Data[15:8] Data[7:0]
Data[23:16]
Write Command[0]
SCK Active
HiZ
Write Command[1]
SCK
SDI
SDO
SSB
Figure 4-4: Single Word Write Access Timing
50 Rev 3