Datasheet

73S8023C Data Sheet DS_8023C_019

4 Rev. 1.5

Figures

Figure 1: 73S8023C Block Diagram ............................................................................................................. 2

Figure 2: Power Down Mode Operation: CS = high

.................................................................................... 10

Figure 3: Activation Sequence – Synchronous Mode

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Figure 4: Synchronous Deactivation Operation – CKSEL = High

............................................................... 12

Figure 5: Asynchronous Activation Sequence – RSTIN Low When CMDVCC Goes Low

......................... 13

Figure 6: Asynchronous Activation Sequence – Timing Diagram #2

......................................................... 13

Figure 7: Asynchronous Deactivation Sequence

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Figure 8: Timing Diagram – Management of the Interrupt Line OFF

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Figure 9: I/O and I/OUC State Diagram

...................................................................................................... 16

Figure 10: I/O – I/OUC Delays Timing Diagram

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Figure 11: 73S8023C – Typical Application Schematic

.............................................................................. 17

Figure 12: DC – DC Converter efficiency (V

= 5 V) ................................................................................ 20

Figure 13: DC – DC Converter Efficiency (V

= 3 V) ................................................................................ 20

Figure 14: 32-QFN Mechanical Drawing

..................................................................................................... 24

Figure 15: 32-QFN 73S8023C Pin Out

....................................................................................................... 25

Table

Table 1: Choice of VCC Pin Capacitor .......................................................................................................... 8