Datasheet

DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 13
Figure 5: Asynchronous Activation Sequence – RSTIN Low When CMDVCC Goes Low
The following steps list the activation sequence and the timing of the card control signals when the
system controller pulls the CMDVCC low while the RSTIN is high:
1. CMDVCC is set low.
2. Next, the internal V
CC
control circuit checks the presence of V
CC
at t
1
. In normal operation, the
voltage V
CC
to the card becomes valid during this time. If not, OFF goes low to report a fault to the
system controller, and the power V
CC
3. Due to the fall of RSTIN at t
to the card is turned off.
2
4. CLK is applied to the card at the end of t
, turn I/O (AUX1, AUX2) to reception mode.
3
5. RST is to be a copy of RSTIN after t
after I/O is in reception mode.
4
. RSTIN may be set high before t
4
, however the sequencer
won’t set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
IO
CLK
RSTIN
t
1
t
2
t
3
t
4
RST
t
1
= 0.510 ms (timing by 1.5MHz internal Oscillator)
t
2
= 1.5µs, I/O goes to reception state
t
3
= > 0.5µs, CLK active
t
4
Figure 6: Asynchronous Activation Sequence – Timing Diagram #2
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
CMDVCC
VCC
IO
CLK
RSTIN
t
1
t
2
t
3
t
4
RST
t
1
= 0.510 ms (timing by 1.5 MHz internal Oscillator)
t
2
= 1.5 µs, I/O goes to reception state
t
3
≥ 0.5 µs, CLK starts
t
4
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN