Datasheet

73S8023C Data Sheet DS_8023C_019
12 Rev. 1.5
CMDVCC
VCC
IO
OFF
RSTIN
RST
STROBE
CLK
t 0 - Deactivation starts after CMDVCC is set high or OFF falls due to card removal or fault
t
4 - VCC is shut down
(Note: Host should set STROBE low when CMDVCC is set high, otherwise CLK may be truncated.
CLK truncation may occur if an OFF event is triggered)
t
3 - IO falls approx 2us after CLK falls
t 1 - RST falls approx. 0.5us after deactivation begins
t
2 - CLK falls approx. 7.5us after RST falls
-- OR --
t
0 t 1 t 2 t 3
t 5
t 4
t 5 - VCC goes to 0 after discharge of VCC capacitor, approx 100us after deactivation begins
Figure 4: Synchronous Deactivation Operation – CKSEL = High
8.3 Activation Sequence (Asynchronous Mode)
The 73S8023C smart card interface IC has an internal 10 ms delay at power-on reset or upon application
of V
DD
> V
DDF
1. CMDVCC is set low.
or upon exit of Power Down mode. The card interface may only be activated when OFF is
high which indicates a card is present. No activation is allowed at this time. CMDVCC (edge triggered)
must then be set low to activate the card.
The following steps list the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low while the RSTIN is low:
2. Next, the internal V
CC
control circuit checks the presence of V
CC
at the end of t
1
. In normal operation,
the voltage V
CC
to the card becomes valid during t
1
. If V
CC
does not become valid, then OFF goes
low to report a fault to the system controller, and the power V
CC
3. Turn I/O (AUX1, AUX2) to reception mode at the end of t
to the card is turned off.
2
4. CLK is applied to the card at the end of t
.
3
5. RST is a copy of RSTIN after t
.
4
. RSTIN may be set high before t
4
, however the sequencer won’t set
RST high until 42000 clock cycles after the start of CLK.