Datasheet

DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 11
8 Activation and Deactivation
8.1 Activation Sequence (Synchronous Mode)
The 73S8023C smart card interface IC has an internal ~10 ms delay at power-on reset or on application
of V
DD
> V
DDF
1. CMDVCC is set low.
. No activation is allowed at this time. CMDVCC (edge triggered) must then be set low to
activate the card.
The following steps list the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low:
2. Turn on V
CC
and I/O (AUX1, AUX2) to reception mode at the end of (t
ACT
3. RST is a copy of RSTIN and CLK is a copy of STROBE after (t
).
1
).
Figure 3: Activation Sequence – Synchronous Mode
8.2 Deactivation Sequence (Synchronous Mode)
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, V
DD
1. RST goes low at time t
fault and card extraction
during the session and are indicated to the system controller by the fall of OFF.
The following steps list the deactivation sequence and the timing of the card control signals when the
system controller sets the CMDVCC high or a fault condition sets OFF low:
1
2. CLK stops low at time t
.
2
3. I/O goes low at time t
.
3
4. V
. Out of reception mode.
CC
is shut down at time t
4
. After a delay t
5
(discharge of the V
CC
capacitor), V
CC
is low.
CMDVCC
VCC
IO
CLK
RSTIN
t
ACT
t
1
RST
STROBE
t
ACT
~= 500µs
t
1
> 0.5
µ
s after t
ACT
, RST = RSTIN, CLK = STROBE