Datasheet
73S8014RN Data Sheet DS_8014RN_014
6 Rev. 1.0
Table 1 provides the 73S8014RN pin names, pin numbers, type, equivalent circuits and descriptions.
Table 1: 73S8014RN 20-Pin SOP Pin Definitions
Pin Name
Pin
Number
Type
Equivalent
Circuit
Description
Card Interface
I/O 14 IO Figure 14
Card I/O: Data signal to/from card. Includes an 11K pull-up
resistor to V
CC.
RST 15 O Figure 13 Card reset: provides reset (RST) signal to card.
CLK 17 O Figure 12
Card clock: provides clock signal (CLK) to card. The rate of this
clock is determined by the external crystal frequency or
frequency of the external clock signal applied on XTALIN and
CLKDIV selections.
PRES 19 I Figure 16
Card Presence switch: active high indicates card is present.
Includes a high-impedance pull-down current source.
VCC 18 PSO Figure 11
Card power supply – logically controlled by sequencer, output of
LDO regulator. Requires an external filter capacitor to the card
GND.
GND 16 GND – Card ground.
Host Processor Interface
CMDVCC
6 I Figure 16
Command VCC (negative assertion): Logic low on this pin
causes the LDO regulator to ramp the V
CC
supply to the card
and initiates a card activation sequence, if a card is present.
5V/#V 7 I Figure 16
5 volt / 3 volt card selection: Logic high selects 5 volts for V
CC
and card interface, logic low selects 3 volt operation. When the
part is to be used with a single card voltage, this pin should be
tied to either GND or V
DD
. However, it includes a high
impedance pull-up resistor to default this pin high (selection of
5V card) when not connected. This pin shall not be changed
when CMDVCC is low.
CLKDIV1
CLKDIV2
20
5
I Figure 16
Sets the divide ratio from the XTAL oscillator (or external clock
input) to the card clock. These pins include a pull-up resistor for
CLKDIV1 and CLKLDIV2 to provide a default rate of divide by
two.
CLKDIV1 CLKDIV2 CLOCK RATE
0 0 XTALIN/6
0 1 XTALIN/4
1 1 XTALIN/2
1 0 XTALIN
OFF 1 O Figure 10
Interrupt signal to the processor. Active Low - Multi-function
indicating fault conditions and card presence. Open drain output
configuration – It includes an internal 20kΩ pull-up to V
DD.
RSTIN 2 I Figure 16 Reset Input: This signal is the reset command to the card.
I/OUC 3 IO Figure 15
System controller data I/O to/from the card. Includes an 11K
pull-up resistor to V
DD.