Datasheet

73S8014RN Data Sheet DS_8014RN_014
18 Rev. 1.0
3.8 Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of
hardware faults. Hardware faults are over-current, V
DD
fault, V
CC
fault, and card extraction during the session.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
- RST goes low at the end of t
1
.
- CLK is set low at the end of t
2
.
- I/O goes low at the end of t
3
. Out of reception mode.
- V
CC
is shut down at the end of time t
4
. After a delay t
5
(discharge of the V
CC
capacitor), V
CC
is low.
RST
CLK
I/O
VCC
t
1
t
2
t
3
t
4
t
5
CMDVCC
-- OR --
OFF
t
1
= > 0.5μs, timing by 1.5MHz internal Oscillator
t
2
= > 7.5μs
t
3
= > 0.5μs
t
4
= > 0.5μs
t
5
= depends on V
CC
filter capacitor.
For NDS application, C
F
=1μF makes t
1
+ t
2
+ t
3
+ t
4
+ t
5
< 250μs
Figure 6: Deactivation Sequence