Datasheet

DS_8014RN_014 73S8014RN Data Sheet
Rev. 1.0 17
The following steps show the activation sequence and the timing of the card control signals when the system
controller pulls the CMDVCC low while the RSTIN is high:
- CMDVCC is set low at t
0
.
- V
CC
will rise to the selected level and then the internal V
CC
control circuit checks the presence of V
CC
at
the end of t
1
. In normal operation, the voltage V
CC
to the card becomes valid before t
1
. If V
CC
is not valid
at t
1
, the OFF goes low to report a fault to the system controller, and V
CC
to the card is shut off.
- At the fall of RSTIN at t
2
, CLK is applied to the card
- RST is a copy of RSTIN after t
2
.
CMDVCC
VCC
I/O
CLK
RSTIN
t
1
t
2
t
0
RST
t
1
= 0.510 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state)
t
2
= RSTIN goes low and CLK becomes active
t
3
= > 0.5μs, CLK active, RST to become the copy of RSTIN
Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low