Datasheet

DS_8009R_056 73S8009R Data Sheet
Rev. 1.3 7
Pin
Name
Pin
(SO28)
Pin
(QFN20)
Type Description
I/OUC 5 1 I/O System controller data I/O to/from the card. Includes a pull-
up resistor to V
DD.
AUX1UC 6 NA I/O System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V
DD.
AUX2UC 7 NA I/O System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V
DD.
CMDVCC%
CMDVCC#
8
9
2
3
I
I
Logic low on one or both of these pins will cause the LDO to
ramp the Vcc supply to the smart card and smart card
interface to the value described in the following table:
CMDVCC%
CMDVCC#
V
CC
Output Voltage
0 0 1.8 V
0 1 5.0 V
1 0 3.0 V
1 1 LDO off
Refer to for additional information on the CMDVCC% and
CMDVCC# operation.
RSTIN 10 4 I Reset Input. This signal is the reset command to the card.
RDY 12 6 O Signal to controller indicating the 73S8009R is ready
because V
CC
is above the required value after CMDVCC%
and/or CMDVCC# is asserted low. A 20 KΩ pull-up resistor
to V
DD
is provided internally. The pull-up is disabled in
PWRDN and CS=0 modes.
PWRDN 13 7 I
PWRDN=1 puts the circuit into low-power mode with all
analog functions disabled. The circuit will recover from the
PWRDN state in the same manner as recovery from a POR
event, taking approximately 1 ms. PWRDN assertion when
either CMDVCC% or CMDVCC# is low has no effect and is
ignored. There is no pull-up or pull-down provided on this pin.