Datasheet

73S8009R Data Sheet DS_8009R_056
14 Rev. 1.3
3.2 System Controller Interface
Four separate digital inputs allow direct control of the card interface from the host as follows:
• Pin CS: Enables the system controller interface.
• Pin CMDVCC# and/or CMDVCC%: When low, starts an activation sequence.
• Pin RSTIN: Controls the card Reset signal (when enabled by the sequencer).
Other functions are controlled as follows:
• PWRDN places the 73S8009R in a low power mode and shuts down all functions.
• The card clock is completely controlled by CLKIN.
• Vcc output voltage valid is indicated on the RDY pin.
• Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about
the card presence only (low = no card in the reader).
When CMDVCC is set low (Card activation sequence requested from the host), a low level on OFF
means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal /
over-current fault). This condition automatically initiates a deactivation sequence.
3.3 Power Supply and Voltage Supervision
The Teridian 73S8009R smart card interface IC incorporates a LDO voltage regulator. The voltage
output is controlled by the digital input sequence on CMDVCC# and CMDVCC%. This regulator is able to
provide either 1.8 V, 3 V or 5 V card voltages from the power supply applied on the VPC pin.
Digital circuitry is powered by the power supply applied on the VDD pin. V
DD
also defines the voltage
range to interface with the system controller.
Three voltage supervisors constantly check the presence of the voltages V
DD
, V
PC
and V
CC
. A card
deactivation sequence is forced upon a fault detected by any of these voltage supervisors.
The voltage regulator can provide a card current of 65 mA in compliance with EMV 4.1, and of at least
90 mA in compliance with ISO7816-3. The V
CC
voltage supervisor threshold values are defined from the
EMV standard.
3.4 Card Power Supply
The card power supply is internally provided by the LDO regulator. The signals CMDVCC# and
CMDVCC% control the turn-on, output voltage value, and turn-off of V
CC
. When either signal is asserted
low, V
CC
will ramp to the selected value or if both signals are asserted low (within 400 ns of each other),
V
CC
will ramp to 1.8 volts. These signals are edge triggered. If CMDVCC% is asserted low (to command
V
CC
to be 5 V) and at a much later time (greater than 2 µs, typically), CMDVCC# is asserted low, it will be
ignored (and vice versa).
At the assertion (low) of either or both CMDVCC#/CMDVCC% signals, V
CC
will rise to the requested value.
When V
CC
rises to an acceptable value, and stays above that value for approximately 20 µs, RDY will be
set high. Approximately 510 µs after the fall of CMDVCC#/CMDVCC% the circuit will check the see if V
CC
is at or above the required minimum value (indicated by RDY=1) and if not, will begin an emergency
deactivation sequence. During the 510 µs time, over-temperature, card removal, or de-assertion of
CMDVCC#/CMDVCC% shall also initiate an emergency deactivation sequence.