Datasheet
73S8009C Data Sheet DS_8009C_025
8 Rev. 1.5
Pin
Name
Pin
(QFN32)
Type
Equivalent
Circuit
Description
VBUS 23
Alternate power source input from USB connector or
hub.
LIN 27 PSI
Figure 13
Connection to 10 µH inductor for internal step up
converter. Note: inductor must be rated for 400 mA
maximum peak current.
VP 15 PSO
Figure 13 Intermediate output of main converter circuit. Requires
an external 4.7 µF low ESR filter capacitor to GND.
GND 28,31
– Ground.
Microcontroller Interface
CS
12
I
Figure 18
When CS = 1, the control and signal pins are configured
normally. When CS is set low, CMDVCC%, RSTIN, and
CMDVCC# are latched. I/OUC, AUX1UC, and
AUX2UC are set to high-impedance pull-up mode and
do not pass data to or from the smart card. Signals
RDY and OFF are disabled to prevent a low output and
the internal pull-up resistors are disconnected.
OFF 32 O
Figure 12
Interrupt signal to the processor. Active Low - Multi-
function indicating fault conditions and card presence.
Open drain output configuration – It includes an internal
20 kΩ pull-up to V
DD.
Pull-
up is disabled in Power down
state and CS = 0 modes.
I/OUC 1 IO Figure 17
System controller data I/O to/from the card. Includes a
pull-up resistor to V
DD.
AUX1UC 2 IO Figure 17
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V
DD.
AUX2UC 3 IO Figure 17
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V
DD.
CMDVCC%
CMDVCC#
4
5
I
I
Figure 18
Logic low on one or both of these pins will cause the
LDO to ramp the Vcc supply to the smart card and
smart card interface to the value described in the
following table.
CMDVCC% CMDVCC# Vcc Output Voltage
0 0 1.8 V
0 1 5.0 V
1 0 3.0 V
1 1 LDO Off
Note: See the description of the Card Power Supply for
more detail on the operation of CMDVCC% and
CMDVCC#.
RSTIN 6 I
Figure 18 Reset Input: This signal is the reset command to the
card.
RDY 8
Figure 12 Signal to controller indicating the 73S8009C is ready
because V
CC
is above the required value after
CMDVCC% and/or CMDVCC# is asserted low. A 20 kΩ
pull-up resistor to V
DD
is provided internally. Pull-up is
disabled in Power down state and CS=0 modes.