Datasheet

73S8009C Data Sheet DS_8009C_025
14 Rev. 1.5
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Reset and Clock for card interface, RST, CLK
V
OH
Output level, high
I
OH
=-200 µA
0.9 * V
CC
–
V
CC
V
V
OL
Output level, low
I
OL
=200 µA
0
–
0.15
*V
CC
V
V
INACT
Output voltage when
outside of session
I
OL
= 0
–
–
0.1 V
I
RST_LIM
Output current limit, RST
–
–
30 mA
I
CLK_LIM
Output current limit, CLK
–
–
70 mA
t
R
, t
F
Output rise time, fall time C
L
= 35pF for CLK, 10% to
90%
–
–
12 ns
C
L
= 200pF for RST, 10% to
90%
–
–
100 ns
δ
Duty cycle for CLK
C
L
=35pF, F
CLK
≤ 20 MHz,
CLKIN duty cycle is 48% to
52%.
45
–
55
%
2.4 Digital Signals Characteristics
Table 5 lists the 73S8009C digital signals characteristics.
Table 5: Digital Signals Characteristics
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Digital I/O
(except for I/OUC, AUX1UC, AUX2UC; see
Smart Card Interface Requirements
for those specifications)
V
IL
Input Low Voltage -0.3
–
0.8 V
VIL
OFFACK
Input low voltage for
OFF_ACK pin
OFF_REQ pin = VDD -0.3
–
0.7 V
V
IH
Input High Voltage 1.8
–
V
DD
+ 0.3 V
V
OL
Output Low Voltage I
OL
= 2 mA
–
0.45 V
V
OH
Output High Voltage I
OH
= -1 mA V
DD
- 0.45
–
V
R
OUT
Pull-up resistor;
OFF,
RDY
14
20
26
kΩ
R
ACK
Resistor between
OFF_REQ and 0FF_ACK
70 100 130
kΩ
|I
IL1
| Input Leakage Current GND < V
IN
< V
DD
–
–
5 μA
t
SL
Time from CS goes high to
interface active
50
–
–
ns
t
DZ
Time from CS goes low to
interface inactive, Hi-Z
50
–
–
ns
t
IS
Set-up time, control
signals to CS rising edge
50
–
–
ns
t
SI
Hold time, control signals
from CS rising edge
–
–
50
ns
t
ID
Set-up time, control
signals to CS fall
50
–
–
ns
t
DI
Hold time, control signals
from CS fall
–
–
50 ns