Datasheet

DS_1215F_003 73S1215F Data Sheet

Rev. 1.4 97

External Smart Card Control Register (SCECtl): 0xFE0B Å 0x00

Used to directly set and sample signals of External Smart Card interface. There are three modes of

asynchronous operation, an “automatic sequence” mode, and bypass mode. Clock stop per the ISO

7816-3 interface is also supported but firmware must handle the protocol for SIO and SCLK for I

C clock

stop and start. Control for Reset (to make RST signal), activation control, voltage select, etc. should be

handled via the I

C interface when using external 73S73S8010x devices. USR(n) pins shall be used for

C4, C8 functions if necessary.

Table 91: The SCECtl Register

MSB LSB

– – SIO SIOD – – SCLKLVL SCLKOFF

Bit Symbol Function

SCECtl.7 –

SCECtl.6 –

SCECtl.5 SIO

External Smart Card I/O. Bit when read indicates state of pin SIO for

SIOD = 1 (Caution, this signal is not synchronized to the MPU clock), when

written, sets state of pin SIO for SIOD = 0. Ignored if not in bypass or sync

modes. In sync mode, this bit will contain the value of IO pin on the latest

rising edge of SCLK.

SCECtl.4 SIOD

1 = input, 0 = output. External Smart Card I/O Direction control. Ignored if

not in bypass or sync modes.

SCECtl.3 –

SCECtl.2 –

SCECtl.1 SCLKLVL

Sets the state of SCLK when disabled by SCLKOFF bit. If in bypass mode,

this bit directly controls the state of SCLK.

SCECtl.0 SCLKOFF

0 = SCLK enabled, 1 = SCLK disabled. When disabled, SCLK level is

determined by SCLKLVL. This bit has no effect if in bypass mode.