Datasheet

DS_1215F_003 73S1215F Data Sheet
Rev. 1.4 7
Table 181: The RLength Register ............................................................................................................. 108
Table 182: Smart Card SFR Table ........................................................................................................... 109
Table 183: The VDDFCtl Register ............................................................................................................ 110
Table 185: Order Numbers and Packaging Marks ................................................................................... 133
D+
SMART
CARD
ISO
INTERFACE
SCLK
SIO
EXTERNAL
SMART
CARD
INTERFACE
VCC
CONTROL
LOGIC
LED
DRIVERS
GND
VDD
TBUS1
TBUS2 TBUS3
TBUS0
RXTX ERST
ISBR
TCLK
TXD
RXD
LED1 LED2 LED0
ICE INTERFACE
SEC
SMART CARD LOGIC
ISO UART and CLOCK GENERATOR
FLASH/ROM
PROGRAM
MEMORY
64KB
DATA
XRAM
2KB
CORE
SERIAL
VDD
INT2
INT3
GND
GND
PERIPHERAL
INTERFACE
and SFR LOGIC
FLASH
INTERFACE
TEST
OCDSI
ISR
WATCH-
DOG
TIMER
PMU
PORTS
TIMER_0_
1
MEMORY_
CONTROL
CONTROL
UNIT
RAM_
SFR_
CONTROL
ALU
D-
RESET
VOLTAGE REFERENCE
AND FUSE TRIM
CIRCUITRY
VPD REGULATOR
LED3
USB I/O
and
LOGIC
ANA_IN
PLL
and
TIMEBASES
VDD
CPUCLK
SCRATCH
IRAM
256B
12MHz
OSCILLATOR
X12OUT
X12IN
COL4
COL3
COL2
COL1
COL0
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
KEYPAD
INTERFACE
I
2
C
MASTER
INT.
SDA
SCL
USR(8:0)
DRIVERS
USR7
USR6
USR5
USR4
USR3
USR1
USR2
USR0
USR8
32kHz
OSCILLATOR
X32OUT
X32IN
RTC
VCC
RST
CLK
I/O
AUX2
AUX1
PRES
PRESB
VPC
Pins avaiable on both 68 and 44 pin packages.
Pins only avaiable on 68 pin package.
GND
Figure 1: IC Functional Block Diagram