Datasheet

DS_1215F_003 73S1215F Data Sheet
Rev. 1.4 33
1.7.3 Interrupts
The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1 and
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
These will be described in more detail in the respective sections.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
the 73S1215F, for example the USB interface, USR I/O, RTC, smart card interface, analog comparators,
etc. The external interrupt configuration is shown in
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
the 73S1215F, for example the USB interface, USR I/O, RTC, smart card interface, analog comparators,
etc. The external interrupt configuration is shown in
Figure 8. Figure 8.
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
These will be described in more detail in the respective sections.
USR
Int
Ctl
USR
Int
Ctl
USR
Int
Ctl
SCInt
Wait Timeout
Card Event
RxData
TX_Event
Tx_Sent
TX_Error
RX_Error
Card_Det
VCC_OK
CRDCtl
VccCTL
+
SCIE
VCC_TMR
RTC
USB
Analog
Comp
KeyPad
I
2
C
USR
Int
Ctl
t0
t1
int0
int1
USR
Pads
USR0
USR7
USR6
USR5
USR4
USR3
USR2
USR1
INT2
INT3
INT
Pads
int2
int3
Serial
Ch 0
Serial
Ch 1
SerChan 0 int
SerChan 1 int
int4
INT5Ctl
INT6Ctl
int5
int6
+
During STOP, IDLE when
PWRDN bit is set
MPU
CORE
VDD_Fault
+
Delay
Clear PWRDN bit
PDMUXCtl
1
0
Figure 8: External Interrupt Configuration