Datasheet

DS_1215F_003 73S1215F Data Sheet
Rev. 1.4 5
Tables
Table 1: 73S1215F Pinout Description ......................................................................................................... 8
Table 2: MPU Data Memory Map ................................................................................................................ 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Program Security Registers .......................................................................................................... 17
Table 6: IRAM Special Function Registers Locations ................................................................................. 18
Table 7: IRAM Special Function Registers Reset Values ........................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 20
Table 9: PSW Register Flags ...................................................................................................................... 22
Table 10: PSW Bit Functions ...................................................................................................................... 22
Table 11: Port Registers ............................................................................................................................. 23
Table 12: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 25
Table 13: The MCLKCtl Register ................................................................................................................ 25
Table 15: The MPUCKCtl Register ............................................................................................................. 26
Table 17: The INT5Ctl Register .................................................................................................................. 29
Table 19: The MISCtl0 Register .................................................................................................................. 29
Table 21: The MISCtl1 Register .................................................................................................................. 30
Table 23: The MCLKCtl Register ................................................................................................................ 31
Table 25: The PCON Register .................................................................................................................... 32
Table 27: The IEN0 Register ....................................................................................................................... 34
Table 29: The IEN1 Register ....................................................................................................................... 35
Table 31: The IEN2 Register ....................................................................................................................... 35
Table 33: The TCON Register .................................................................................................................... 36
Table 35: The T2CON Register .................................................................................................................. 36
Table 37: The IRCON Register ................................................................................................................... 37
Table 39: External MPU Interrupts .............................................................................................................. 37
Table 40: Control Bits for External Interrupts .............................................................................................. 38
Table 41: Priority Level Groups ................................................................................................................... 38
Table 42: The IP0 Register ......................................................................................................................... 38
Table 43: The IP1 Register ......................................................................................................................... 39
Table 44: Priority Levels .............................................................................................................................. 39
Table 45: Interrupt Polling Sequence .......................................................................................................... 39
Table 46: Interrupt Vectors .......................................................................................................................... 39
Table 47: UART Modes ............................................................................................................................... 40
Table 48: Baud Rate Generation ................................................................................................................ 40
Table 49: The PCON Register .................................................................................................................... 41
Table 51: The BRCON Register ................................................................................................................. 41
Table 53: The MISCtl0 Register .................................................................................................................. 42
Table 55: The S0CON Register .................................................................................................................. 43
Table 57: The S1CON Register .................................................................................................................. 44
Table 59: The TMOD Register .................................................................................................................... 45
Table 61: Timers/Counters Mode Description ............................................................................................ 46
Table 62: The TCON Register .................................................................................................................... 47
Table 64: The IEN0 Register ....................................................................................................................... 48
Table 66: The IEN1 Register ....................................................................................................................... 48
Table 68: The IP0 Register ......................................................................................................................... 49
Table 70: The WDTREL Register ............................................................................................................... 49
Table 72: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 50
Table 73: UDIR Control Bit .......................................................................................................................... 50
Table 74: Selectable Controls Using the UxIS Bits ..................................................................................... 50
Table 75: The USRIntCtl1 Register ............................................................................................................ 51
Table 76: The USRIntCtl2 Register ............................................................................................................ 51
Table 77: The USRIntCtl3 Register ............................................................................................................ 51
Table 78: The USRIntCtl4 Register ............................................................................................................ 51
Table 79: The RTCCtl Register ................................................................................................................... 53
Table 81: The 32-bit RTC Counter .............................................................................................................. 54
Table 82: The 24-bit RTC Accumulator ...................................................................................................... 54