Datasheet

73M1903 Data Sheet DS_1903_032
8 Rev. 2.1
2 Control and Status Registers
Table 2 shows the memory map of addressable registers in the 73M1903. Each register and its bits are
described in detail in the following sections.
Table 2: Memory Map
Address Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00 08h ENFE Unused TXBST1 TXBST0 TXDIS RXG1 RXG0 RXGAIN
01 00h TMEN DIGLB ANALB INTLB Reserved RXPULL SPOS HC
02 FFh GPIO7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0
03 FFh DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
04 00h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
05 00h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
06 10h Rev3 Rev2 Rev1 Rev0 Unused Reserved Reserved Reserved
07 00h Unused
Reserved
Reserved Reserved Reserved Reserved Reserved Reserved
08 00h Pseq7 Pseq6 Pseq5 Pseq4 Pseq3 Pseq2 Pseq1 Pseq0
09 0Ah Prst2 Prst1 Prst0 Pdvsr4 Pdvsr3 Pdvsr2 Pdvsr1 Pdvsr0
0A 22h Ichp3 Ichp2 Ichp1 Ichp0 FL Kvco2 Kvco1 Kvco0
0B 12h Unused Ndvsr6 Ndvsr5 Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0
0C 00h Nseq7 Nseq6 Nseq5 Nseq4 Nseq3 Nseq2 Nseq1 Nseq0
0D C0h Xtal1 Xtal0 Reserved Reserved Unused Nrst2 Nrst1 Nrst0
0E 00h Frcvco PwdnPLL Reserved Unused Unused Unused Unused Unused
0F-7F Unused Unused Unused Unused Unused Unused Unused Unused
To prevent unintended operation, do not write to reserved or unused locations. These locations are for
factory test or future use only and are not intended for customer programming.