Datasheet

71M6543F/71M6543G Data Sheet
96 v2
5 Firmware Interface
5.1 I/O RAM Map –Functional Order
In Table 68 and Table 69, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’.
Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with
an ‘R’, and must always be written with a zero. Writing values other than zero to reserved bits may have undesirable side effects and must be
avoided. Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected
to the VBAT pin.
The I/O RAM locations listed in Table 68 have sequential addresses to facilitate reading by the MPU (e.g., in order to verify their contents). These
I/O RAM locations are usually modified only at boot-up. The addresses shown in Table 68 are an alternative sequential address to the addresses
from Table 69 which are used throughout this document. For instance, EQU[2:0] can be accessed at I/O RAM 0x2000[7:5] or at I/O RAM
0x2106[7:5].
Table 68: I/O RAM Map – Functional Order, Basic Configuration
Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CE6
2000
EQU[2:0]
U
CHOP_E[1:0]
RTM_E
CE_E
CE5
2001
U
SUM_SAMPS[12:8]
CE4
2002
SUM_SAMPS[7:0]
CE3 2003
U
CE_LCTN[6/5:0]
CE2
2004
PLS_MAXWIDTH[7:0]
CE1
2005
PLS_INTERVAL[7:0]
CE0
2006
DIFF6_E
DIFF4_E
DIFF2_E
DIFF0_E
RFLY_DIS
FIR_LEN[1:0]
PLS_INV
RCE0
2007
CHOPR[1:0]
RMT6_E
RMT4_E
RMT2_E
TMUXR6[2:0]
RTMUX
2008
U
TMUXR4[2:0]
U
TMUXR2[2:0]
FOVRD
2009
U
U
R
U
U
U
U
U
MUX5
200A
MUX_DIV[3:0]
MUX10_SEL
MUX4
200B
MUX9_SEL
MUX8_SEL
MUX3
200C
MUX7_SEL
MUX6_SEL
MUX2
200D
MUX5_SEL
MUX4_SEL
MUX1
200E
MUX3_SEL
MUX2_SEL
MUX0
200F
MUX1_SEL
MUX0_SEL
TEMP
2010
TEMP_BSEL
TEMP_PWR
OSC_COMP
TEMP_BAT
TBYTE_BUSY
TEMP_PER[2:0]
LCD0
2011
LCD_E
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD1
2012
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]