Datasheet

71M6543F/71M6543G Data Sheet
v2 9
Figure 1: IC Functional Block Diagram
IADC
0
MUX
and
PREAMP
XIN
XOUT
VREF
CKADC
CE
32
-
bit Compute
Engine
MPU
(
80515
)
CE CONTROL
OPT
_
RX
/
SEGDIO
55
OPT
_
TX
/
SEGDIO
51
/
WPULSE
/
VPULSE
RESET
VBIAS
EMULATOR
PORT
3
C
E
_
B
U
S
Y
OPTICAL
INTERFACE
UART
0
TX
RX
X
F
E
R
B
U
S
Y
6
COM
0
..
5
VLC
2
LCD DRIVER
CEDATA
0
x
000
...
0
x
2
FF
PROG
0
x
000
...
0
x
3
FF
DATA
0
x
0000
...
0
xFFFF
PROGRAM
0
x
0000
...
0
xFFFF
0
x
00000
…
0
X1FFFF
DIGITAL I
/
O
CONFIGURATION
RAM
(
I
/
O RAM
)
0
x
2000
...
0
x
20
FF
I
/
O
R
A
M
MEMORY SHARE
0
x
0000
...
0
x
13
FF
16
8
RTCLK
RTCLK
(
32
KHz
)
MUX
_
SYNC
CKCE
CKMPU
CK
32
32
8
8
8
POWER FAULT
DETECTION
4
.
9
MHZ
<
4
.
9
MHz
4
.
9
MHz
GNDD
V
3
P
3
A
V
3
P
3
D
VBAT
Voltage
Regulator
2
.
5
V to logic
VDD
32
KHz
MPU
_
RSTZ
FAULTZ
WAKE
CON
-
FIGURATION
PARAMETERS
GNDA
VBIAS
9
/
20
/
2010
CROSS
CLOCK GEN
Oscillator
32
KHz
CK
32
MCK
PLL
VREF
DIV
ADC
MUX CTRL
STRT
MUX
MUX
CKFIR
RTM
SEGDIO Pins
WPULSE
VARPULSE
WPULSE
VARPULSE
TEST
TEST
MODE
VLC
1
VLC
0
<
4
.
9
MHz
CKMPU
_
2
x
CKMPU
_
2
x
SDCK
SDOUT
SDIN
E
_
RXTX
/
SEG
48
E
_
TCLK
/
SEG
49
E
_
RST
/
SEG
50
FLASH
128
KB
V
3
P
3
A
FIR
EEPROM
INTERFACE
CK
_
4
X
LCD
_
GEN
PB
RTC
VBIAS
MEMORY
SHARE
17
E
_
RXTX
E
_
TCLK
E
_
RST
(
Open Drain
)
ICE
_
E
∆Σ_
AD CONVERTER
+
-
VREF
V
3
P
3
SYS
TEST MUX
VLCD
VLCD
Voltage
Boost
MPU RAM
(
5
KB
)
22
S
P
I
VSTAT
VBAT
_
RTC
IADC
1
IADC
2
IADC
3
IADC
4
IADC
5
IADC
6
IADC
7
VADC
8
(
VA
)
VADC
9
(
VB
)
VADC
10
(
VC
)
SEG Pins
2
TEST MUX
2
Non
-
Volatile
CONFIGURATION
RAM
BAT
TEST
TEMP
SENSOR
RTM