Datasheet

71M6543F/71M6543G Data Sheet
v2 49
Although the oscillator may appear to work when VBAT is not connected, this mode of operation is not re-
commended.
If VBAT_RTC is connected to a drained battery or disconnected, a battery test that sets
TEMP_BAT may drain the supply connected to VBAT_RTC and cause the oscillator to stop. A
stopped oscillator may force the device to reset. Therefore, an unexpected reset during a battery
test should be interpreted as a battery failure.
2.5.3 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz crystal oscillator output that is multiplied by a PLL by
600 to obtain 19.660800 MHz, the master clock (MCK). All on-chip timing, except for the RTC clock, is
derived from MCK. Table 41 provides a summary of the clock functions and their controls.
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see 2.4.6
Timers and Counters).
The master clock can be boosted to 19.66 MHz by setting the PLL_FAST bit = 1 (I/O RAM 0x2200[4]) and
can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CKMPU is determined by
another divider controlled by the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) and can be
set to MCK*2
-(MPU_DIV+2)
where MPU_DIV[2:0] may vary from 0 to 4. When the ICE_E pin is high, the
circuit also generates the 9.83 MHz clock for use by the emulator.
The PLL is only turned off in SLP mode or in LCD mode when LCD_BSTE is disabled. The LCD_BSTE
value depends on the setting of the LCD_VMODE [1:0]
field (see Table 51).
When the part is waking up from SLP or LCD modes, the PLL is turned on in 6.29 MHz mode, and the
PLL frequency is not be accurate until the PLL_OK (SFR 0xF9[4]) flag rises. Due to potential overshoot, the
MPU should not change the value of PLL_FAST until PLL_OK is true.
Table 41: Clock System Summary
Clock
Derived
From
Fixed Frequency or Range
Function
PLL_FAST
=1
PLL_FAST
=0
Controlled by
OSC
Crystal
32.768 kHz
–
Crystal clock
MCK Crystal/PLL
19.660800 MHz
(600*CK32)
6.291456 MHz
(192*CK32)
PLL_FAST
Master clock
CKCE
MCK
4.9152 MHz
1.5728 MHz
–
CE clock
CKADC MCK
4.9152 MHz,
2.4576 MHz
1.572864 MHz,
0.786432 MHz
ADC_DIV
ADC clock
CKMPU MCK
4.9152 MHz …
307.2 kHz
1.572864 MHz…
98.304 kHz
MPU_DIV[2:0]
MPU clock
CKICE MCK
9.8304 MHz…
614.4 kHz
3.145728 MHz …
196.608 kHz
MPU_DIV[2:0]
ICE clock
CKOPTMOD MCK 38.40 kHz 38.6 kHz –
Optical
UART
Modulation
CK32
MCK
32.768 kHz
–
32 kHz clock
2.5.4 Real-Time Clock (RTC)
2.5.4.1 RTC General Description
The RTC is driven directly by the crystal oscillator and is powered by either the V3P3SYS pin or the
VBAT_RTC pin, depending on the V3OK internal bit. The RTC consists of a counter chain and output
registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month,
month, and year. The chain registers are supported by a shadow register that facilitates read and write
operations.
Table 42 shows the I/O RAM registers for accessing the RTC.