Datasheet

71M6543F/71M6543G Data Sheet
v2 43
Interrupt Enable Interrupt Flag
Interrupt Description
Name Location Name Location
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
2700[2]
2700[4]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR E8[2]
SFR E8[4]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[6]
SFR F8[5]
RTC_1MIN interrupt (int 6)
RTC_T interrupt (int 6)
SPI interrupt
EEPROM interrupt
CE_Xpulse interrupt (int 2)
CE_Ypulse interrupt (int 2)
CE_Wpulse interrupt (int 2)
CE_Vpulse interrupt (int 2)
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 33.
Table 33: Interrupt Priority Level Groups
Group
Group Members
0
External interrupt 0
Serial channel 1 interrupt
1
Timer 0 interrupt
External interrupt 2
2
External interrupt 1
External interrupt 3
3
Timer 1 interrupt
External interrupt 4
4
Serial channel 0 interrupt
External interrupt 5
5
–
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 34) by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in
IP1(SFR 0xB9) (Table 35). If requests of the same priority level are received simultaneously, an internal
polling sequence as shown in Table 36 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 34: Interrupt Priority Levels
IP1[x] IP0[x] Priority Level
0
0
Level 0 (lowest)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest)
Table 35: Interrupt Priority Registers (IP0 and IP1)
Register Address
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
IP0
SFR 0xA9
–
–
IP0[5]
IP0[4]
IP0[3]
IP0[2]
IP0[1]
IP0[0]
IP1
SFR 0xB9
–
–
IP1[5]
IP1[4]
IP1[3]
IP1[2]
IP1[1]
IP1[0]