Datasheet

71M6543F/71M6543G Data Sheet
40 v2
Referring to Figure 12, interrupt sources can originate from within the 80515 MPU core (referred to as
Internal Sources) or can originate from other parts of the 71M6543 SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of Figure 12, and in Table 25 and
Table 26 (i.e., EX0-EX6).
Interrupt Overview
When an interrupt occurs, the MPU vectors to the predetermined address as shown in Table 37. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from instruction, RETI. When an RETI is performed, the processor returns to the
instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor also indicates this by setting a flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when
the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt is
acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions
are met:
• No interrupt of equal or higher priority is already in progress.
• An instruction is currently being executed and is not completed.
• The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
• The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 25, Table 26 and Table 27).
• The Timer/Counter control registers, TCON and T2CON (see Table 28 and Table 29).
• The interrupt request register, IRCON (see Table 30).
• The interrupt priority registers: IP0 and IP1 (see Table 35).
Table 25: The IEN0 Bit Functions (SFR 0xA8)
Bit Symbol Function
IEN0[7]
EAL
EAL = 0 disables all interrupts.
IEN0[6]
–
Not used.
IEN0[5]
–
Not used.
IEN0[4]
ES0
ES0 = 0 disables serial channel 0 interrupt.
IEN0[3]
ET1
ET1 = 0 disables timer 1 overflow interrupt.
IEN0[2]
EX1
EX1 = 0 disables external interrupt 1.
IEN0[1]
ET0
ET0 = 0 disables timer 0 overflow interrupt.
IEN0[0]
EX0
EX0 = 0 disables external interrupt 0.
Table 26: The IEN1 Bit Functions (SFR 0xB8)
Bit Symbol Function
IEN1[7]
–
Not used.
IEN1[6]
–
Not used.
IEN1[5]
EX6
EX6
= 0 disables external interrupt 6.
IEN1[4]
EX5
EX5 = 0 disables external interrupt 5.
IEN1[3]
EX4
EX4 = 0 disables external interrupt 4.
IEN1[2]
EX3
EX3 = 0 disables external interrupt 3.
IEN1[1]
EX2
EX2 = 0 disables external interrupt 2.
IEN1[0]
–
Not used.