Datasheet

71M6543F/71M6543G Data Sheet
v2 39
Table 23: TMOD Register Bit Description (SFR 0x89)
Bit
Symbol
Function
Timer/Counter 1:
TMOD[7]
Gate
If TMOD[7] is set, external input signal control is enabled for Counter 1. The
TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter 0
to increment. With these settings, Counter 0 increments on every falling
edge of the logic signal applied to one or more of the SEGDIO2-11 pins, as
specified by the contents of the DIO_R2 through DIO_R11 registers. See
2.5.10 Digital I/O and LCD Segment Drivers and Table 46.
TMOD[6]
C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register functions as a timer.
TMOD[5:4]
M1:M0
Selects the mode for Timer/Counter 0 as shown in Table 21.
Timer/Counter 0
TMOD[3]
Gate
If TMOD[3] is set, external input signal control is enabled for Counter 0. The
TR1 bit in the TCON register (SFR 0x88) must also be set in order for Counter 1
to increment. With these settings, Counter 1 increments on every falling
edge of the logic signal applied to one or more of the SEGDIO2-11 pins, as
specified by the contents of the DIO_R2 through DIO_R11 registers. See
2.5.10 Digital I/O and LCD Segment Drivers and Table 46.
TMOD[2]
C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register functions as a
timer.
TMOD[1:0]
M1:M0
Selects the mode for Timer/Counter 1, as shown in Table 21.
Table 24: The TCON Register Bit Functions (SFR 0x88)
Bit Symbol Function
TCON[7]
TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when an
interrupt is processed.
TCON[6]
TR1
Timer 1 run control bit. If cleared, Timer 1 stops.
TCON[5]
TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt
is processed.
TCON[4]
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
TCON[3]
IE1
Interrupt 1 edge flag is set by hardware when the falling edge on external
pin int1 is observed. Cleared when an interrupt is processed.
TCON[2]
IT1
Interrupt 1 type control bit. Selects either the falling edge or low level on
input pin to cause an interrupt.
TCON[1]
IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external
pin int0 is observed. Cleared when an interrupt is processed.
TCON[0]
IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on
input pin to cause interrupt.
2.4.7 WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard hardware watchdog timer instead (see
2.5.13 Hardware Watchdog Timer).
2.4.8 Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own interrupt request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in IEN0 (SFR 0xA8), IEN1
(SFR 0xB8), and IEN2 (SFR 0x9A). Figure 12 shows the device interrupt structure.