Datasheet

71M6543F/71M6543G Data Sheet
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2.3 Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately
measure energy. The CE calculations and processes include:
• Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied by the constant sample time).
• Frequency-insensitive delay cancellation on all channels (to compensate for the delay between
samples caused by the multiplexing scheme).
• 90° phase shifter (for VAR calculations).
• Pulse generation.
• Monitoring of the input signal frequency (for frequency and phase information).
• Monitoring of the input signal amplitude (for sag detection).
• Scaling of the processed samples based on calibration coefficients.
• Scaling of samples based on temperature compensation information.
2.3.1 CE Program Memory
The CE program resides in flash memory. Common access to flash memory by the CE and MPU is
controlled by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space
for the CE program cannot exceed 4096 16-bit words (8 KB). The CE program counter begins a pass
through the CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction
is executed. For proper operation, the code pass must be completed before the multiplexer cycle ends.
The CE program must begin on a 1 KB boundary of the flash address. The I/O RAM control field
CE_LCTN[6/5:0] (I/O RAM 0x2109[6/5:0]) on the 71M6543F and CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) on
the 71M6543G defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is
located at 1024*CE_LCTN[5:0] on the 71M6543F and 1024*CE_LCTN[6:0] on the 71M6543G.
2.3.2 CE Data Memory
The CE and MPU share data memory (RAM). Common access to XRAM by the CE and MPU is controlled
by a memory share circuit. The CE can access up to 3 KB of the 5 KB data RAM (XRAM), i.e. from RAM
address 0x0000 to 0x0C00.
The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE.
The MPU reads and writes the XRAM shared between the CE and MPU as the primary means of data
communication between the two processors.
The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and
accumulators. This hardware is controlled through I/O RAM field EQU[2:0] (equation assist, I/O RAM
0x2106[7:5]), bit DIO_PV (I/O RAM 0x2457[6]), bit DIO_PW (pulse count assist, I/O RAM 0x2457[7]), and
SUM_SAMPS[12:0] (accumulation assist, I/O RAM 0x2107[4:0] and 0x2108[7:0]).
The integration time for each energy output, when using standard CE code, is SUM_SAMPS[12:0] /2184.53
(with MUX_DIV[3:0] = 7, I/O RAM 0x2100[7:4] ). CE hardware issues the XFER_BUSY interrupt when the
accumulation is complete.
2.3.3 CE Communication with the MPU
The CE outputs six signals to the MPU: CE_BUSY, XFER_BUSY, XPULSE, YPULSE, WPULSE and
VPULSE. These are connected to the MPU interrupt service. CE_BUSY indicates that the CE is actively
processing data. This signal occurs once every multiplexer frame. XFER_BUSY indicates that the CE is
updating to the output region of the CE RAM, which occurs whenever an accumulation cycle has been
completed. Both, CE_BUSY and XFER_BUSY are cleared when the CE executes a HALT instruction.
XPULSE and YPULSE can be configured to interrupt the MPU and indicate zero crossings of the mains
voltage, sag failures, or other significant events. Additionally, these signals can be connected directly to DIO
pins to provide direct outputs from the CE. Interrupts associated with these signals always occur on the
leading edge.