Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
128 Rev 4
5.3.6 CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0-3, 9 and 10 (decimal) shown
in Table 79.
The MUX_SEL column in Table 79 shows the MUX_SEL handles for the various sensor input pins. For
example, if differential mode is enable via control bit DIFFA_E = 1 (I/O RAM 0x210C[4]), then the inputs IAP
and IAN are combined together to form a single differential input and the corresponding MUX_SEL handle is
0. Similarly, the CE RAM location column provides the CE RAM address where the sample data is stored.
Continuing with the same example, if DIFFA_E = 1, the corresponding CE RAM location where the
samples for the IAP-IAN differential input are stored is 0 and CE RAM location is not disturbed.
The IB input can be configured as a direct-connected sensor (i.e., directly connected to the 71M654x) or as a
remote sensor (i.e., using a 71M6x01 Isolated Sensor). If the remote sensor is disabled by RMT_E = 0 and
differential mode is enabled by DIFFB_E = 1 (I/O RAM 0x210C[5]), then IBP and IBN form a differential
input with a MUX_SEL handle of 2, and the corresponding samples are stored in CE RAM location 2 (CE
RAM location 3 is not disturbed). If the remote sensor enable bit RMT_E = 1 and DIFFB_E = 0 or 1, then the
MUX_SEL handle is undefined (i.e., the sensor is not connected to the 71M654x, so MUX_SEL does not
apply, see 2.2 Analog Front End (AFE) on page 12), and the samples corresponding to this remote
differential IBP-IBN input are stored in CE RAM location 2 (CE RAM location 3 is not disturbed).
The voltage sensor inputs (VA and VB) do not have any associated configuration bits. VA has a MUX_SEL
handle value of 10, and its samples are stored in CE RAM location 10. VB has a MUX_SEL handle value of 9
and its samples are stored in CE RAM location 9.
Table 79: CE Raw Data Access Locations
ADC
Location
Pin
MUX_SEL Handle
CE RAM Location
DIFFA_E
DIFFA_E
0
1
0
1
ADC0
IAP
0
0
0
0
ADC1
IAP
1
1
RMT_E, DIFFB_E
RMT_E, DIFFB_E
0,0
0,1
1,0
1,1
0,0
0,1
1,0
1,1
ADC2
IBP
2
2 – –
2
2 2* 2*
ADC3
IBN
3
3
There are no configuration bits for ADC9, 10
ADC9
VB†
9
9
ADC10
VA
10
10
Notes:
* Remote interface data.
†
71M6542F/G only.
5.3.7 FCE Status and Control
The CE Status Word, CESTATUS, is useful for generating early warnings to the MPU (Table 80). It contains
sag warnings for phase A and B, as well as F0, the derived clock operating at the fundamental input fre-
quency. The MPU can read the CE status word at every CE_BUSY interrupt. Since the CE_BUSY inter-
rupt occurs at 2520.6 Hz, it is desirable to minimize the computation required in the interrupt handler of
the MPU.
Table 80: CESTATUS Register
CE Address
Name
Description
0x80
CESTATUS
See description of CESTATUS bits in Table 81.
CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful
for generating an early power fail warning to initiate necessary data storage. CESTATUS represents the