Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
Rev 4 111
5.2 I/O RAM Map – Alphabetical Order
Table 76 lists I/O RAM bits and registers in alphabetical order.
Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and
copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk
describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the
NV supply and is not initialized. Write-only bits return zero when they are read.
Locations that are shaded in grey are non-volatile (i.e., battery-backed).
Table 76: I/O RAM Map – Functional Order
Name Location
Rst
Wk Dir Description
ADC_E
2704[4]
0
0
R/W
Enables ADC and VREF. When disabled, reduces bias current.
ADC_DIV
2200[5] 0 0 R/W
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting determines whether MCK is divided by 4 or 8:
0 = MCK/4
1 = MCK/8
The resulting ADC and FIR clock is as shown below.
PLL_FAST = 0
PLL_FAST = 1
MCK
6.291456 MHz
19.660800 MHz
ADC_DIV = 0
1.572864 MHz
4.9152 MHz
ADC_DIV = 1
0.786432 MHz
2.4576 MHz
BCURR
2704[3]
0
0
R/W
Connects a 100 µA load to the battery selected by TEMP_BSEL.
BSENSE[7:0]
2885[7:0]
–
–
R
The result of the battery measurement. See 2.5.6 71M654x Battery Monitor.
CE_E
2106[0]
0
0
R/W
CE enable.
CE_LCTN[5:0]
2109[5:0]
31 31 R/W
CE program location. The starting address for the CE program is
1024*CE_LCTN.
CHIP_ID[15:8]
CHIP_ID[7:0]
2300[7:0]
2301[7:0]
0
0
0
0
R
R
These bytes contain the chip identification.
CHOP_E[1:0]
2106[3:2] 0 0 R/W
Chop enable for the reference bandgap circuit. The value of CHOP changes
on the rising edge of MUXSYNC according to the value in CHOP_E:
00 = toggle
1
01 = positive 10 = reversed 11 = toggle
1
except at the mux sync edge at the end of an accumulation interval.