Datasheet

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004
52 Rev 2
command so the MPU can access the bus. There are no issues with Data RAM access; SPI and the
MPU will share the bus with no conflicts for Data RAM access.
Table 48: I/O RAM Registers Accessible via SPI
Name Address (hex) Bit Range Read/Write
CE0
2000
7:3
RW
CE1
2001
7:0
RW
CE2
2002
5:3, 1:0
RW
CONFIG0
2004
7:6, 1:0
RW
CONFIG1
2005
5:2, 0
RW
VERSION
2006
7:0
R
CONFIG2
2007
7:0
RW
DIO0
2008
7, 4:0
RW
DIO1 to DIO6
2009 to 200E
6:4, 2:0
RW
−
200F
7:6, 3:2
RW
RTM0H
2060
1:0
RW
RTM0L
2061
7:0
RW
RTM1H
2062
1:0
RW
RTM1L
2063
7:0
RW
RTM2H
2064
1:0
RW
RTM2L
2065
7:0
RW
RTM3H
2066
1:0
RW
RTM3L
2067
7:0
RW
PLS_W
2080
7:0
RW
PLS_I
2081
7:0
RW
SLOT0 to SLOT9
2090 to 209A
7:0
RW
CE3
209D
3:0
RW
CE4
20A7
7:0
RW
CE5
20A8
7:0
RW
WAKE
20A9
7:5, 3:0
R
CONFIG3
20AC
7:0
RW
CONFIG4
20AD
7:0
RW
−
20AF
2:0
RW
SPI0
20B0
4, 0
RW
SPI1
20B1
4, 0
R
VERSION
20C8
7:0
R
CHIP_ID
20C9
7:0
R
TRIMSEL
20FD
4:0
RW
TRIMX
20FE
0
RW
TRIM
20FF
7:0
RW