Datasheet

Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005
30 Rev 2
1.4.8 WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard watchdog timer instead (see 1.5.16
Hardware Watchdog Timer).
1.4.9 Interrupts
The 80515 MPU provides 11 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0 (SFR 0xA8),
IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A). Figure 8 shows the device interrupt structure.
Referring to Figure 8, interrupt sources can originate from within the 80515 MPU core (referred to as
Internal Sources) or can originate from other parts of the 71M653x SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of Figure 8 , and in Table 24 and
Table 25 (i.e., EX0-EX6).
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 36. Once
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from instruction, RETI. When an RETI is performed, the processor will return to
the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is
set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, after that, samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt
will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following
conditions are met:
• No interrupt of equal or higher priority is already in progress.
• An instruction is currently being executed and is not completed.
• The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
• The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 24, Table 25 and Table 26.
• The Timer/Counter control registers, TCON and T2CON (see Table 27 and Table 28).
• The interrupt request register, IRCON (see Table 29).
• The interrupt priority registers: IP0 and IP1 (see Table 34).
Table 24: The IEN0 Bit Functions (SFR 0xA8)
Bit
Symbol
Function
IEN0[7]
EAL
EAL = 0 disables all interrupts.
IEN0[6]
WDT
Not used for interrupt control.
IEN0[5]
–
Not Used.
IEN0[4]
ES0
ES0 = 0 disables serial channel 0 interrupt.
IEN0[3]
ET1
ET1 = 0 disables timer 1 overflow interrupt.
IEN0[2]
EX1
EX1 = 0 disables external interrupt 1.
IEN0[1]
ET0
ET0 = 0 disables timer 0 overflow interrupt.
IEN0[0]
EX0
EX0 = 0 disables external interrupt 0.