Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 119
Appendix B: Revision History
Revision
Date
Description
2
March 26, 2013
1) Added Guaranteed By Design notes to the Electrical Specifica-
tions (Section 5).
2) Added explanation on NV properties of RTCA_ADJ[ ] and
PREG/QREG[ ] (Section 1.5.3) and corrected entries in Table 55.
3) Added note that transitions to BROWNOUT mode must be avoid-
ed during page erase operations (Section 1.5.5).
4) Added note in Application Section 3.1 stating that filter com-
ponents other that those shown on the Demo Boards should not
be connected to the sensor input pins. Added reference to
AN5292.
5) Consolidated spelling of low-power modes (SLEEP, BROWN-
OUT) and of COMPSTAT register.
6) Corrected value for C2 capacitor in Table 68.
7) Extended explanation of WD_OVF (not preserved in SLEEP
mode) and corrected entries in Table 55.
8) Added explanation of WD_NROVF_FLAG (Section 1.4.9).
9) Added explanation of MPU activity on transition to BROWNOUT
mode in Section 2.4.2.
10) Swapped the order of the Individual Flags and Individual Enable
Bits in Figure 8.
1.3 June 9, 2010 1) Throughout document: Added bit ranges to all register fields where
missing (e.g. MPU_DIV[2:0]).
2) Figure 1, Figure 2: corrected name for PSDI and PSDO signals.
3) 1.4 80515 MPU Core
Added SFR register addresses where needed.
(Page 19) Table 6: Change approximate frequencies to exact
frequencies.
(Page 19) Changed providing Library to providing demonstration
source code.
(Page 20) Added note about MUX_DIV=0 disables ADC output.
(Page 21) See restrictions on INTBITS register.
(Page 22) Added P1-P3 to Table 10.
(Page 23) Updated Data Pointer description.
(Page 24) Table 14: Updated description for FWCOL0, FWCOL1.
(Page 26) 1.4.6 UARTs: Clarified SOBUF, S1BUF as Tx and Rx
buffers.
(Page 27) Added caution on proper way to clear flag bits.
(Page 30) 1.4.9 Interrupts: Clarified External vs Internal interrupts.
(Page 31) Table 25: Added Interrupt sources for Ext. Interrupts 2-6.
4) 1.5.2 Internal Clocks
(Page 36) Table 37: Changed frequencies to exact frequencies.
(Page 38) Added caution concerning frequency relationship to
specific CE code.
5) 1.5.3 Real-Time Clock (RTC): (Page 39) Added description for
observing RTC timing on TMUXOUT pin, corrected values for
RTCA_ADJ, and achievable frequency step.
6) 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and
71M6532D/F (Page 45):
Added caution about not sourcing current in or out of DIO pins.
Updated Figure 10 : Connecting an External Load to DIO Pins.
7) 1.5.13 Battery Monitor (Page 46
): Corrected RAM address for
ADC
data.
8) 1.5.15 SPI Slave Port (page 49): Clarified description of I/O RAM