Datasheet

71M6521DE/DH/FE Data Sheet
Page: 96 of 107 Rev 3
TIMING SPECIFICATIONS
RAM AND FLASH MEMORY
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
CE DRAM wait states
CKMPU = 4.9 MHz
5
Cycles
CKMPU = 1.25 MHz
2
Cycles
CKMPU = 614 kHz 1 Cycles
Flash Read Pulse Width
V3P3A=V3P3SYS=0
BROWNOUT MODE
30
100 ns
Flash write cycles
-40°C to +85°C
20,000
Cycles
Flash data retention
25°C
100
Years
Flash data retention
85°C
10
Years
Flash byte writes between page or mass
erase operations
2 Cycles
FLASH MEMORY TIMING
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Write Time per Byte
42 µs
Page Erase (512 bytes)
20 ms
Mass Erase
200 ms
EEPROM INTERFACE
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Write Clock frequency (I
2
C)
CKMPU=4.9 MHz, Using
interrupts
78 kHz
CKMPU=4.9 MHz, “bit-
banging” DIO4/5
150 kHz
Write Clock frequency (3-wire)
CKMPU=4.9 MHz 500 kHz
RESET and V1
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Reset pulse fall time
1
1
µs
Reset pulse width
5
µs
1
Guaranteed by design; not production tested.
RTC
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Range for date
2000
-
2255
year