Datasheet

71M6521DE/DH/FE Data Sheet
Page: 74 of 107 Rev 3
RTM Probes:
RTM0
2060
RTM0[7:0]
RTM1
2061
RTM1[7:0]
RTM2
2062
RTM2[7:0]
RTM3
2063
RTM3[7:0]
Pulse Generator:
PLS_W
2080
PLS_MAXWIDTH[7:0]
PLS_I
2081
PLS_INTERVAL[7:0]
SFR MAP (SFRs Specific to the Teridian 80515) – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use
and should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers
Name
SFR
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Digital I/O:
DIO7
80
DIO_0[7:4] (Port 0)
Reserved
DIO_0[2:1]
PB
DIO8
A2
DIO_DIR0[7:4]
Reserved
DIO_DIR0[2:1]
Reserved
DIO9
90
DIO_1[7:6]
Reserved
DIO_1[3:0] (Port 1)
DIO10
91
DIO_DIR1[7:6]
Reserved
DIO_DIR1[3:0]
DIO11
A0
Not Used
Not Used
DIO2[5:3] (QFN-68) *
Reserved
DIO_2[1:0] (Port 2)
DIO12
A1
Not Used
Not Used
DIO_DIR2[5:3] (QFN-68) *
Reserved
DIO_DIR2[1:0]
Interrupts and WD Timer:
INTBITS
F8
INT6
INT5
INT4
INT3
INT2
INT1
INT0
IFLAGS E8
IE_PLLFALL
WD_RST
IE_PLLRISE IE_WAKE IE_PB IE_FWCOL1 IE_FWCOL0 IE_RTC IE_XFER
Flash:
ERASE
94
FLSH_ERASE[7:0]
FLSHCTL
B2
PREBOOT
SECURE
Not Used
Not Used
Not Used
Not Used
FLSH_MEEN
FLSH_PWE
PGADR
B7
FLSH_PGADR[6:0]
Not Used
Serial EEPROM:
EEDATA
9E
EEDATA[7:0]
EECTRL
9F
EECTRL[7:0]
* = Only available on QFN-68 package. Reserved in LQFP-64 package.